Abstract: This article introduced one kind based on the FPGA sampling speed 60Mbit/s double channel simple digital oscilloscope design, can realize the measuring range and the sampling frequency automatic control, the data buffer, the demonstration as well as with computer’s between data transmission.
Key word: Data acquisition; Digital oscilloscope; FPGA
Introduction
Although the traditional oscilloscope the function is complete, but the volume is big, the weight is heavy, the cost is high, and so on a series of questions caused the application to be restricted. Taking this into consideration, portable digital storage gathering arises at the historic moment, it has used the LCD demonstration, the high speed A/D gathering and the transformation, the ASIC chip and so on new technology, has the very strong usability and the giant market potential, also has represented the present age electronic surveying instrument’s one kind of trend of development, namely are many to the function, the volume is small, the weight is light, easy to operate hand-held instrument development.
System composition structure and principle of work
System’s hardware part for together high speed data acquisition circuit wafer. It can realize the bi-pass magical skill according to the input, each group sampling frequency may achieve 60Mbit/s. May divide into from the function the hardware system: Front end the signal the enlargement and the recuperation module, the high speed a/d conversion module, the FPGA logical control module, the monolithic integrated circuit control module, the USB data transmission module, the liquid crystal display and the keyboard control and so on several parts, its structural style as shown in Figure 1.
Figure 1 system principle structure drawing
Input signal after pre-amplification and gain adjustable circuit switching, becomes conforms to a/D switch request input voltage, transforms after A/D the digital signal, from the FPGA in FIFO buffer, passes through the USB connection to transmit in again the computer, for more data processing, or directly the signal demonstration which will gather from the monolithic integrated circuit control on the liquid crystal screen.
High speed data gathering module
This system may realize double channel synchro data gathering, moreover each channel’s gathering speed must achieve 60Mbit/s, considered that should maintain to two group data acquisitions the synchronization parallel, therefore uses each channel in the design to have the sampling retainer and a/D switch alone. Selects MAXIM Corporation MAX1197 a/D switch, it is a model of double channel, the 3.3V power supply, each channel 60Mbit/s sampling frequency modulus switch chip. Its internal integration two-circuit difference wide band sampling retainer and a/D switch, may output the lock to save, have the low power loss, light-sized, the high dynamic property characteristic.
This system’s measurement voltage’s scope may achieve ±300V, will use on the cro coupling and the circuit wafer the differential pressure method the input signal will carry on 1:1 either 10:1 or 100:1 weaken first, will then satisfy a/D switch’s input voltage scope request again through the following electric circuit processing.
Was measured that signal output signal which obtains through the general probe head and the voltage divider, because the output impedance is high, needs to pass through the impedance conversion into low output impedance, maintains the signal the integrity. At the same time, says regarding a system, the overload is inevitable, in overloads in the situation, if has not protected, the component is very easy to damage. Therefore, in the system has designed by the diode and the resistance constitution over-load protection electric circuit, the input signal will limit between ±4.8V scope. Regarding the impedance conversion, chooses ADI Corporation’s high performance FET the input univoltage feedback amplifier AD8065 chip, the constitution follower realizes the impedance conversion. After impedance conversion signal, but must through the gain control, in be able to cause to input satisfies A/D to a/D switch’s voltage the input voltage request, uses the analog switch and the wide band precision amplifier coordination, by analog switch selection different turning on resistance value, thus realizes the different enlargement factor, serves purpose which the program control enlarges. Gain control electric circuit as shown in Figure 2, the input protection and impedance inverter circuit as shown in Figure 3.
Figure 2 gain control electric circuit
Figure 3 input protection and impedance inverter circuit
FPGA control unit
Programmable logical component FPGA is ASIC which one-and-a-half kinds have custom-made, it allows the electric circuit designer to program voluntarily realizes the specific application function. This design has used the schematic diagram input and the VHDL language inputs two different methods, the control unit load bearing majority of control duty, provides the corresponding control signal for each functional module to guarantee the overall system work the accuracy. Realizes the following several aspect function specifically:
The frequency dividing circuit and produces a/D switch’s control signal
This data acquisition system, has the quite wide measuring range, in a FPGA internal design frequency dividing circuit, has used for to realize in view of the different frequency was measured that the signal choice different sampling frequency, guaranteed the gathering data is more precise. The frequency division unit uses the graph input method to realize its internal structure drawing as shown in Figure 4. In Figure 4, uses the T trigger when the input is 1, each clock along arrival when the output can have the jump to realize the frequency division. Simultaneously we may see, the T trigger’s input has some logical combination constitution, this constituted the gating clock. Regarding the gating clock, analyzes the clock function carefully, avoids the burr the influence. But gating clock when satisfies the following two conditions, then may guarantee that the clock signal does not present the dangerous the burr, the gating clock may look like the overall situation clock equally reliable work.
· actuates clock’s logic to only contain one “and” the gate either “or” the gate. If uses any attachment to patrol under certain active status, will present the burr which the competition will produce.
· a logical gate input takes the actual clock, but this logical gate possesses other inputs to regard the address or the pilot wire, they observe are opposite and maintain in clock’s establishment the time the restraint.
Regarding this design’s in A/D switch, its control signal has two: Clock input signal CLK and enables output signal OE. The CLK signal inputs 60M directly through the active crystal oscillator the signal, but OE signal through the FPGA interior after CLK frequency synchronism clock signal opposition obtains, like this just may satisfy a/D switch’s transformation succession relations.
Figure 4 frequency dividing circuit interior structure drawing
Figure 5 frequency dividing circuit and frequency selective network mark chart
The above frequency dividing circuit and the frequency selective network and a/D switch’s control signal produced the electric circuit to produce logical symbol as shown in Figure which in the top layer corresponded 5.
FIFO function unit design
This system’s A/D sampling speed is quite high, the sampling period achieves 16.7ns, but selects Hua Bang company monolithic integrated circuit 77E58, in the crystal oscillator 40MHz read-write cycle is 100ns, moreover main line’s transmission speed is also quite low, therefore both are unable in the speed to match. In this case, must establishes the corresponding cushion way between high speed gathering and low speed processing to be able guarantee system’s normal work. Therefore joins one in a/D switch and among the monolithic integrated circuit processor to enter first leaves type buffer (FIFO) first, alleviates between the high speed signal and the low speed equipment’s connection is contradictory. In this design uses EAB which in EP1K50QC208 brings (embedded logical block), tool produces two 512*8 position directly through Quartus II LPM FIFO, takes two group A/D switch’s data buffering. Quartus in II produces the graphics symbol and its succession profile graph as shown in Figure 6. The FIFO input signal has the data feeds signal, directly with A/D switch’s input connected under; Writes a letter the number and writes enables the signal, writes a letter the number and the above frequency selection signal is connected, may read in by the appropriate speed the data FIFO, writes enables to establish to be forever effective; Reads the signal and reads enables the signal, this has the control signal which the monolithic integrated circuit sends out to give; The asynchronous reset signal before each time is writing FIFO its clear spatial. The output signal has the data signal, is connected with monolithic integrated circuit’s data line, transmits the data; Full symbol signal, when is effective stops writing the operation to FIFO; Spatial symbol signal, when is effective stops reading the operation to FIFO.
Figure 6 FIFO graphics symbol and its succession oscillogram
Figure 7 frequency measurement module mark chart
Frequency measurement module design
Figure 8 pair of channel profile demonstration
The frequency measurement module is playing the very vital role in this system, it is not only deciding the sampling frequency, but also decides the liquid crystal display screen’s basic time datum. The survey frequency is in the unit interval/unit time counting actually. In this design, the frequency measurement module’s concrete design mentality is: After first transforms a/D switch the data through a comparator obtains the frequency measurement pulse, because in this design’s A/D the 0V voltage transformation is 0×80, to avoid nearby 0V the small signal vibration creating the frequency measurement error, comparator’s fixed correlative value hypothesis is 0×88. Then frequency measurement pulse after a D trigger synchronization then starts to count, to avoid the peaked pulse or the burr signal in the counting process creates to the counting the influence, according to the previous frequency measurement’s result choice appropriate filtration pulse width, namely compared to will assign the pulse width small signal pulse not to count, enhanced the entire survey precision. Entire frequency measurement module’s mark chart as shown in Figure 7. In Figure 7, compare is the comparison module, after then passes through the trigger synchronization, after pulse width filtration module (FreLatch1) to counting frequency measurement module (MeasureFrequency), the data which the survey obtains through eight register counter_out1, counter_out2 and the counter_out3 output. The OneSecondPulse module to have the 1s pulse module, provides the datum reference impulse for the counting.
Liquid crystal display and keyboard module
In this design, we select built-in SED1335 controller’s liquid crystal display module MS320240B, the resolution are 320*240. Not only may independent carry on the text to demonstrate or graphical display, but may also carry on the graph text synthesis way demonstration. Can measure in this system the signal the profile, two verniers and the profile crossing point voltage value and the time value demonstration in the liquid crystal box. In liquid crystal box demonstration as shown in Figure 8.
In realizes in the man-machine communication function monolithic integrated circuit correspondence input device, what simple is switching matrix constitution keyboard which is composed of the pressed key, it momentarily may issue each kind of control command and carry on the data feeds. Usually the pressed key uses for the mechanical switch, has many shortcomings, mainly will be presses a key is pressed down or the ball will get up when will have the slight vibration, the vibration time and switch’s physical characteristics related, generally will be 5ms~10ms. In order to avoid in the vibration period scanning keyboard obtaining the wrong good value and a row value, generally after examining has the key presses down time delay 10ms to carry on the scanning again. In this design, uses 3*8 the determinant keyboard, sends out each kind to order to carry on to gathering is similar to the oscilloscope button’s operation.
Figure 9 simple oscilloscope’s superior machine control panel
USB correspondence unit
This design uses Cypress Corporation’s CY7C68013 chip to realize the USB transmission module design, CY7C68013 conforms to the USB2.0 standard chip. Gives through the USB main line the gathering data real-time transmission the computer, is advantageous for the superior machine also to be possible the real-time demonstration profile, but may also the very convenient stored datum.
Superior machine application programming
Uses the computer formidable computing power and the graph environment in the superior machine, establishes presente in figures and diagrams the soft kneading board to substitute conventional the instrument control kneading board. On the soft kneading board has with the actual instrument similar switch, the indicating lamp and other control portion. The user operates the soft kneading board through the mouse or the keyboard, testing instrument’s performance and the feasibility. At the same time, the user does not use the compilation test order, may be possible to carry on the test, the survey, has realized the test automation, the intellectualization.
Uses the LabVIEW compilation superior machine chart application procedure in this design. Simple oscilloscope’s superior machine control panel as shown in Figure 9, it mainly realizes the double channel profile demonstration function. Demonstrated that the kneading board uses the vernier to carry on the voltage and the time survey, may reduce the artificial error in reading to enhance the survey accuracy. When two channels simultaneously demonstrate, may “the current port select” the button choose channel’s parameter which through the front panel on must demonstrate. The RUN/STOP pressed key can start and stop the data acquisition display module, is advantageous for the operation and the reading. The front panel also has hauls with the reproduce by pantograph button, facilitates examines the graph.
Conclusion
This article is based on the FPGA simple digital oscilloscope system’s hardware/software’s design mentality and the design proposal. After this system design completes, the test indicated that the system may the data which gathers through the software routine control transform the corresponding profile to demonstrate, demonstrated profile and input signal profile basic consistent, can realize the data acquisition, the buffer, the transmission and the profile demonstration and so on portable gathering system’s basic function, has the very broad application prospect.
Reference:
1. Shen sweet flag, high speed data gathering system’s principle and application, Beijing: People’s posts and telecommunications publishing house, 1995
2. Zhao Xinmin, smart instrument design basis, Harbin Industry University Publishing house, 1999
3. Liu Quan and so on, portable 20M digital storage oscilloscope, electronic manufacture, in 2005 the 4th issue
4. the Wang Cheng Confucian, Li of imposing appearance, USB2.0 principle and project development, Beijing: Defense industry Publishing house, 2004
