Abstract: Introduced one kind of programmable planned target phase shifting thyristor triggering circuit, uses FPGA (the scene programmable gate array) the chip, uses the VHDL hardware description language programming. This electric circuit has the foreword auto-adapted function, the stability is good, is suitable for three-phase all controls the rectification, the accent to press the situation.
Key word: Electronic installation automation; Thyristor; Digital phase shifting triggering; VHDL; Foreword from suitable
Introduction
The phase shifting trigger is controls the thyristor electric power electronic installation an important part, its performance fit and unfit quality direct relation entire electric power electronic installation performance index, thus is always valued people’s. In the past the commonly used simulation triggering circuit had many shortcomings, brought inconveniently many for the debugging and the use. , The digital phase shifting triggering technological development extremely was in recent years rapid, appeared take the monolithic integrated circuit, the special-purpose microprocessor as well as the programmable gate array as the core many kinds of trigger integrated circuit. This article uses ALTERA Corporation’s EPF10K10 chip, used the VHDL language design one kind take the entire digital phase shifting technology as the core, to have the foreword auto-adapted as well as presses in view of the accent with the rectification pattern recognition function double pulse row type three-phase thyristor digit phase shifting triggering circuit.
1 three-phase thyristor controls the triggering circuit principle of work
Triggering circuit’s major function is realizes according to the mains locking signal as well as the control signal to the thyristor phase shifting control.
Regarding three-phase all controls the rectification or the accent presses the electric circuit, the request order output trigger pulse is separated in turn 60°. This design selects the three-phase synchronized absolute triggering method. According to the single-phase synchronized signal’s rise along with the drop along, forms two synchronized spots, sends out two phase mutual deviation 180° trigger pulse separately. Then by belongs to the three-phase this kind of electric circuit to be composed the pulse to form the unit to output 6 groups pulses, passes through again makes up the pulse to form and the allocation units forms makes up the pulse and outputs 6 groups pulses according to the order.
Figure 1
2 EDA design realization
This unit module (pulse forms, modulation and protection) including PULSE the module and PULSE_ASSIGN (makes up pulse to form and pulse assignment) the module. The entire electric circuit forms the electric circuit by three group of same single-phase trigger pulses to be composed, compares the positive and negative two group trigger pulse respectively, 6 groups pulses after make up the pulse to form and the assignment module form 6 groups double to make up the pulse output narrowly. Rise which (either b_input, c_input) inputs according to synchronized signal a_input along or drop along arrival time, uses nine counter countings. When the counting value and the pulse_input end (phase control signal input end) inputs the value is equal, then outputs the corresponding trigger pulse. Carries on the frequency division the external connection system clock to carry on the modulation as the modulating pulse to the trigger pulse. When protects carries the pulse_enable input is `1 ‘, does not output the trigger pulse, is `0 ‘ when the normal output, realizes the protection function by this. Basic principle diagram as shown in Figure 1.
2.1 PULSE modules
This module completes the pulse to form, the modulation and the protection function. Inferior modular circuit as shown in Figure 2, divides into 4 parts, namely a part transforms synchronization control signal impulse Syn_A into the positive and negative half period synchronization control level.
The B part completes the phase shifting function. C255 is 255 enters the system the counter, its clock Clk2 is 25kHz, the counting result carries on the comparison through comparator T1 and T2 and input phase control signal data. Realizes the phase shifting function by this.
The C part through 25 enters system counter C25 to realize the pulse width to form the function. May also change the pulse width through the online change internal parameter.
The D part realizes the pulse-duration modulation function.
Below gives B the part VHDL hardware description language procedure:
LIBRARYieee;
USEieee.std_logic_1164.all;
USEieee.std_logic_arith.all;
USEieee.std_logic_unsigned.all;
ENTITYpulseIS
PORT
(clk2:instd_logic;
syn_output1:instd_logic;
syn_output2:instd_logic;
pulse_data:instd_logic_vector(7downto0);
out1, out2:outstd_logic
);
ENDpulse;
ARCHITECTUREaOFpulseIS
signalout1, out2:std_logic;
signalcount1, count2:std_logic_vector(7downto0);
BEGIN
pulse_generator1:process(clk2)
begin
IFsyn_output1=’0′THEN
count1<= ” 11111110 “;
out1<=’0′;
elsif (clk2′eventandclk2=’1′)then
count1<=count1-1;
if(count1>pulse_data)then
out1<=’0′;
else
out1<=’1′;
count1<= ” 00000000 “;
endif;
endif;
ENDPROCESSpulse_generator1;
pulse_generator2:process(clk2)
begin
IFsyn_output2=’1′THEN
count2<= ” 11111110 “;
out2<=’0′;
elsif (clk2′eventandclk2=’1′)then
count2<=count2-1;
if(count2>pulse_data)then
out2<=’0′;
else
out2<=’1′;
count2<= ” 00000000 “;
endif;
endif;
ENDPROCESSpulse_generator2;
enda;
2.2 PULSE_ASSIGN modules
This module completes makes up the pulse to form and the pulse allocation function. In order to guarantee after the rectification bridge switches on, the common cathode group and altogether the anode group respectively has a thyristor electric conduction, must be supposed a breakover pair of thyristor simultaneously to send the trigger pulse to two groups. For example when requests the VT1 breakover, besides sends the trigger pulse to VT1, but must simultaneously send a trigger pulse to VT6; When triggers VT2, must give VT1 simultaneously to send a trigger pulse and so on.
Makes up the pulse to form the plan to be as follows:
out1<=in1orin6;
out2<=in6orin3;
out3<=in3orin2;
out4<=in2orin5;
out5<=in5orin4;
out6<=in4orin1;
And: in1, in2, in3, in4, in5, in6 corresponds PULSE separately the module a positive and negative pulse, the B positive and negative pulse, the C positive and negative pulse output. out1, out2, out3, out4, out5, out6 outputs in the correspondence leveling circuit’s 1-6 thyristors.
3 simulations and experimental result
In order to examine the above design the validity and the feasibility, pressed the procedure software simulation, the single-phase actual circuit testing and the three-phase closed-loop system separately has carried on the examination to this trigger’s performance, and has obtained the good simulation and the experimental result.
3.1 simulation results
Software has carried on the simulation using ALTERA Corporation’s MAXPLUSII to the above procedure. Figure 3 is 6 group trigger pulse electric circuit’s simulation profile. a_input, b_input and c_input respectively are the gap 120° three-phase lock input signals; 1,2,3,4,5,6 distinctions correspond 1-6 thyristor gate trigger output signal extremely, obviously this result is quite ideal.
3.2 single-phase experiments test the profile
In view of the above simulation result, composed the hardware experiment electric circuit to carry on the test. Figure 4 has given when the model control angle A phase synchronism signal and corresponding 1 thyristor trigger pulse profile. In order to cause the profile to be clearer, here gives has not carried on the modulation the trigger pulse profile.
4 in three-phase rectification system’s application situation
Applies the fore-mentioned trigger pulse to form the electric circuit and arranges the procedure constitution three-phase thyristor trigger, uses in three-phase all controlling in the rectification system. Uses the thyristor model PK55F120 which produces for the Japanese three society electrical machinery companies, resistive load. The result obtains the output voltage the continual adjustment, the accent presses the scope to be possible to adjust from 0V to specified output voltage 510V, the correspondence trigger control angle Alpha for 0°~120°, the experiment had proven this trigger may the steady operation, its adjustment output be continuously smooth, the effect is satisfying. In Figure 5 (a) and (b) gave separately obtained through the Hall voltage pick-up α=60° and α=0° three-phase has all controlled leveling circuit’s output wave shape.
5 conclusions
In summary, the application three-phase mains locking, take the FPGA component as a core, through the software online programming’s method, may manufacture the three-phase foreword auto-adapted thyristor trigger. The theoretical analysis and the simulation and the experimental result have proven this three-phase trigger design simple feasible. This method causes the entire trigger’s function to realize with a piece of integrated circuit chip, thus antijamming ability, and the hardware and the software are very economical, it in has the broad application prospect primarily without a doubt by in the thyristor power component’s electric power electron convertor equipment.
