1 introduction
The phase-locked loop in domain applications and so on correspondence, radar, survey and automated control is extremely widespread, already became in each kind of electronic installation the essential basic part. Develops along with the electronic technology to the digitized direction, needs to use the digital form to realize signal phase-lock processing. Therefore, obtained more and more attention to the entire digital phase-locked loop’s research and the application.
The traditional digital phase-locked loop system is the hope through uses has the low pass characteristic ring circuit filter, obtains the stable vibration control data. Regarding the higher order entire digit phase-locked loop, its digital filter use frequently based on the DSP arithmetic circuit. This kind of structure phase-locked loop, when the ring circuit band width is very narrow, the ring circuit filter will realize will need the very big electric circuit quantity, this for on specific IC’s application and piece system SOC (system on chip) the design will bring certain difficulty. Another type’s entire digital phase-locked loop is uses the pulse train low-pass filtering counting circuit to take the ring circuit filter, after like paces back and forth stochastically the sequence filter, first N, M sequence filter and so on. These electric circuits through the phase error pulse which produces to the phase demodulation module carry on the counting operation, obtains the controllable oscillator module the vibration controlled variable. Because the pulse train low-pass filtering method of attributes is quite complex misalignment treating processes, carries on the linear approximation with difficulty, therefore, is unable to use the system transfer function the analysis method determination phase-locked loop design variable. Cannot realize to higher order digit phase-locked loop performance index Xie Ou controls and the analysis, is unable to meet the high application need.
This article proposed one kind based on the proportion integral (PI) the control algorithm higher order entire digit phase-locked loop. Has given this phase-locked system’s concrete structure, has established the system mathematical model, and has carried on the theoretical analysis to its system performance. Used the MATLAB software to carry on the simulation experiment to the system. Using the EDA technical design this phase-locked system, and realized with FPGA.
2 entire digital phase-locked loop structure and principle of work
Based on proportional-plus-integral control algorithm’s third-order entire digital phase-locked loop’s system structure as shown in Figure 1. This system by the digital discriminator (DPD), the digital ring circuit filter (DLF) and the numerical control oscillator (DCO) three parts is composed.
Figure 1 third-order entire digital phase-locked loop system structure drawing
In because this phase-locked system the numerical control oscillator uses accumulator’s structure, therefore, the accumulator outputs the parallel code is numerical control oscillator’s output phase code B, it has reflected between the input signal and the output signal instantaneous phase difference. In the discriminator register is constitutes by a group of D trigger. DCO output phase code B parallel delivers D trigger’s D end, in input signal’s forward zero crossing to the D trigger sampling, D trigger group’s output E expresses this sampling time instantaneous phase difference, thus has completed the digital phase demodulation function.
The digital ring circuit filter’s leading role is the noise elimination and the high frequency component, and is controlling the speed which and the precision the loop phase adjusts. In order to enhance phase-locked system’s performance, has designed based on the PI control algorithm second-order digital filter. Its principle of work is to the discriminator output phase error signal after the first-order integration element, the second-order integration element and the proportional component adjustment, produces integral control parameter NP1 and NP2 separately, as well as proportional control parameter NI, then takes sum of these three controlled variable to take the numerical control oscillator’s controlled variable. In order to cause the control code group which DLF outputs in identical instantaneous parallel to send in DCO, turns on a cushion register between these two ring circuit part.
The numerical control oscillator is the accumulator which constitutes by the full adder and the register composes. If the accumulator position length is N, then low position input end NL meets DLF control code group G, top digit NH meets DCO free oscillation frequency 0 f control code group C (this parameter to be possible by designer hypothesis). When control code group G is `0 ‘, DCO the out-port highest order AN output signal’s frequency is DCO free oscillation frequency f0. In the ring circuit locking process, control code group G is not is zero, this time accumulator’s accumulation result will carry changes accumulator’s frequency division coefficient, thus changes the DCO output signal the frequency, realizes the proportional-plus-integral control parameter to local to estimate the signal the control action, serves phase-lock’s purpose finally.
3 digital phase-locked loop system performance theoretical analysis
3.1 phase-locked loop system structures
If the sampling period is very short, and the digital discriminator, the digital ring circuit filter and the numerical control oscillator’s gain factor combines the ring circuit overall gain to consider together, may draw the phase-locked loop in Z territory system structure as shown in Figure 2.
Figure 2 θi (Z) is the phase-locked loop input signal; θo (Z)? For phase-locked loop output signal; K is the ring circuit overall gain; Ka is the proportional component coefficient; Kb is the first-order integration element coefficient; Kc is the second-order integration element coefficient.
May write this phase-locked loop split-ring, the closed loop and the erroneous Z territory transfer function separately by Figure 2:
3.2 phase-locked loop system’s stable state analysis
3.2.1 system’s stabilities
May know by discrete system’s Naikuisite criterion, the loop system stable full essential condition is the closed loop transfer function characteristic root must be located at the Z plane completely in the unit circle, so long as has one outside the unit circle, the system is unstable. (2) may result in ring circuit’s secular equation by the type is:
Using Zhu Li (Jury) the stability criterion, may according to the system closed loop characteristic equation coefficient distinguish whether the characteristic root is located at the Z plane in the unit circle, thus distinction system to be whether stable. May result in after the analysis inferential reasoning, this third-order digital phase-locked loop system stable all conditions are:
3.2.2 system trace errors
May calculate ring circuit’s under each kind of different input signal function stable state error of tracking by the system error transfer function, namely:
θi (Z) is the input signal, He(Z) is the phase-locked system error transfer function. This system which (6) obtains by the type corresponds in each kind of typical phase input signal stable state error of tracking is listed in Table 1.
May know by Table 1, this phase-locked system regarding the phase step, the frequency step and the frequency rises the input signal the stable state error of tracking is zero slanting.
4 phase-locked system’s design realizes with the simulation
Based on Figure 1 the phase-locked loop system’s structure, uses Xilinx Corporation’s ISE design software, uses the modulation design method from the top, carries on the programming design separately with VHDL to entire digital phase-locked loop’s each part, then makes the integrated design and the simulation to this system. Finally, uses Xilinx Corporation’s sparnⅡThe series FPGA component has realized phase-locked system’s hardware function.
This phase-locked system’s design variable is as follows: In the discriminator the D trigger’s position length is 16; In DLF in two integration elements accumulator’s position long is 16; In DCO accumulator’s position length is 24, accumulator’s clock rate fclk is 8MHz, proportion integral control code group’s word length G=14, free oscillation frequency f0 control code group’s word length C=10.
Chooses different scale-up factor Ka and integral coefficient Kb, Kc, may change K1, K2, the K3 parameter value, then may act according to this phase-locked system’s stability condition type (5), the judgment system is whether stable. Table 2 have listed the phase-locked system stability analyses result which several kind of typical parameters correspond.
In table 2 supposes
According to this system in the Z territory’s transfer function and Table 2 design variable K1, K2, K3, carries on the analysis using the MATLAB software, obtains third-order entire digital phase-locked loop under unit step signal function system simulation curve as shown in Figure 3.
System simulation curve may see from Figure 3, the simulation experiment with theoretical analysis’s result is consistent. The adjustment proportion and the integral coefficient not can only control phase-locked system’s stability, but may also control system’s phase-lock speed. Obviously, at maintains under the system stable condition, Figure 3(d) the design variable corresponds the system phase-lock speed is quick.
According to this system in the Z territory’s error transfer function and the actual design variable, may obtain the system separately, in the phase step, the frequency step and the frequency rise under the signal function response curve as shown in Figure 4 slanting. From Figure 4 may see that the system regarding the above signal’s stable state error of tracking is zero. The conclusion which obtains with the theoretical analysis is also consistent. Overall evaluation performance indices and so on phase-locked system’s stability, stable state difference and phase-lock speed, choose design variable K1 finally = 2-3, K2 = 2-6, K3 = 2-11.
Figure 5 gave has used the EDA technical design the third-order entire digital phase-locked loop system simulation profile, in the chart clkin is the system clock signal, clr is the system reset signal, ui is the input signal, uo is the output signal, uo1 is the doubled frequency output signal, uo2 is four frequency multiplication output signal. From Figure 5 obviously, this phase-locked system may simultaneously obtain the frequency multiplication output signal.
Figure 6 has given the third-order entire digital phase-locked loop hardware circuit test profile which realizes with FPGA. The system simulation and the hardware test result indicated that this system can realize the phase-lock function.
4 conclusions
This article proposed one kind based on the PI control algorithm’s third-order entire digital phase-locked loop, uses the EDA technology to carry on the system design, and realizes with the programmable logical component. This phase-locked loop has the circuit structure to be simple, the control is flexible, the tracking accuracy is high, the ring circuit performance good, easy to integrate characteristic. Surpass in the phase-lock speed and the stable aspect use the digit phase-locked system which existing the pulse train low-pass filtering method of attributes realizes. The theoretical analysis and the simulation experiment indicated that the change proportional-plus-integral control parameter, may adjust phase-locked system’s phase-lock speed and the stability very conveniently, thus simplified the design process. The hardware test result confirmed that can realize its phase-lock function using the EDA technical design’s higher order entire digit phase-locked loop. This phase-locked loop may insert in SoC as the functional module, provides fast, stable and the high accuracy synchronized signal for each kind of control system.
