Introduction
The conference telephone is an telecommunication digital switching system’s important service, this service may realize between many users also to talk over the telephone. The former conference telephone uses the special-purpose chip to realize mostly, along with the DSP technology’s progress, uses general DSP to realize the conference telephone, because has the capacity to be big, the cost is low, promotion nimble and so on merits, becomes the first choice plan gradually.
TI Corporation low power loss high performance’s DSP TMS320VC5410 has 3 independent data buses and 1 program bus, provides highly parallelism, its multichannel cushion serial port McBSP (Multichannel Buffered Serial Port) may in the connection digital switching system the commonly used ST-BUS link, the DMA controller be possible maximum limit to reduce DSP very easily internal CPU the holding time, on the piece RAM may provide the program run space and the McBSP receiving and dispatching data buffer conveniently, therefore in this article uses this DSP to realize the conference telephone function.
The algorithm design realizes
The conference telephone realizes may use the maximum value output law. This method is the telephone conversation all quarters voice scope which arrives at the identical frame in carries on the comparison, generally is the speech person’s scope is biggest, after discovering the scope biggest voice and the scope second big voice, gives the scope second big voice the speech person, but gives the scope biggest voice other users. 
Figure 1 maximum value output law conference telephone schematic drawing
Figure 1 is the maximum value output law conference telephone’s schematic drawing. In the chart is take the square conference as the example, after A, B, C, D the four directions Mth PCM code sends in TMS320VC5410, in M 1 frame period carries on the comparison, the hypothesis judges The voice scope to be biggest, B voice scope second big, therefore voice gives the user in M 2 the frame B A, The voice to give B, C, the D three side users, what a user hears is the B user’s sound, what other users hear is a user’s sound.
Figure 2 has given conference telephone’s DSP data processing flow chart.
Figure 2 conference telephone’s DSP data processing flow chart
First DSP simultaneously starts McBSP the receiving and dispatching port, when the McBSP receive port receives Mth which the ST-BUS link sends to correspond to some user time slot 8 bit a law (or the m law, below take our country’s A law code after example) PCM voice data, its extension 13 bit linear codes, then makes up in the linear code right margin 3 bit 0 to give first receive register DRR1, this is because TMS320VC5410 is 16, only could to the piece on RAM according to 16 bit visits, to raise the algorithm efficiency, in the design uses the linear code to carry on the voice scope comparison. After the linear code transformation completes, the McBSP notice assigns for its receive DMA controller, this time, the DRR1 data has been ready, receives the DMA controller to read in immediately this 16 bit data according to its corresponding address in the receive buffer. We in RAM have assigned 2 data buffers respectively on the DSP piece for the McBSP receive and the transmission port. For convenient software processing, when disposes DMA, when assigns achieves for its data buffer half-full and entire is full, to DSP in CPU transmission interrupt, therefore DMA receives the Mth voice data backward CPU transmission interrupt.
When CPU receives the DMA interrupt, indicated that DMA already received the Mth complete time slot data, CPU, in M 1 frame period rests on time slot number which in each conference telephone the attending user corresponds, to saves takes the absolute value less advanced line amplitude relative size in the receive data buffer user’s Mth voice data, found the biggest voice and the second big voice, read in separately them the M 2 frame attending user correspondence in the transmission data buffer address.
When the M 2 frame transmits the DMA controller to read out the corresponding data from its data buffer to give McBSP in turn the transmission port, transmits the port first to transfer this linear code pronunciation data Cheng ALV the pronunciation data, then completes the PCM voice data transmission.
DSP disposition
TMS320VC5410 has 3 McBSP and 6 DMA, may use in conference telephone’s realization completely. May apportion in turn DMA0~2 McBSP0~2 the receive port, DMA3~5 apportions in turn McBSP0~2 the transmission port.
On piece RAM assignment
TMS320VC5410 has 8K on the character 16-bit piece double to visit RAM (DARAM) and 56K on the character 16-bit piece visits RAM (SARAM) only. DARAM is composed of 4, each size is the 2K character. Each may read two times or the read-write in the identical clock cycle each one time, therefore suitable to use between DSP and the Host news buffer, therefore data space’s 0080h-1FFFh mapping is DARAM. SARAM is composed of 7, each size is the 8K character. SARAM may read at the same place in the identical clock cycle, writes another at the same place, therefore suitable to use in the operating procedure area and the data area, procedure space 2000h? The FFFh mapping is SARAM, data space 8000h 蠪 the FFFh mapping is SARAM. The RAM assignment see Figure regarding the piece on 3, the concrete assignment as follows shows:
Figure 3 piece on RAM assignment schematic drawing
1.0×0080~0×1FFF, DSP and Host news buffer.
2.0×2000~0×4FFF, DSP procedure area, including object file .text and .cinit section. And 0×2000~0×2080 is the DSP interrupt to the meter.
3.0×5000~0×7FFF, DSP data area, including DSP document .bss and .stack section.
the 4.0×8000~0×803F, DMA0 buffer, uses in McBSP0 the receive.
the 5.0×8040~0×807F, DMA1 buffer, uses in McBSP1 the receive.
the 6.0×8080~0×80BF, DMA2 buffer, uses in McBSP2 the receive.
the 7.0×80C0~0×80FF, DMA3 buffer, uses in McBSP0 the transmission.
the 8.0×8100~0×813F, DMA4 buffer, uses in McBSP1 the transmission.
the 9.0×8140~0×817F, DMA5 buffer, uses in McBSP2 the transmission.
McBSP disposition
McBSP supports 2M and 8M the ST-BUS link, here we take 4.096M input clock’s 2.048M the ST-BUS link as the examples, see Figure 4 the ST-BUS link schematic drawing. The McBSP disposition mainly involves the following four registers. 
Figure 4 ST-BUS link schematic drawing
1. pin control register (PCR)
CLK(R/X)M = 1, produces the internal receiving and dispatching clock by the internal sampling rate generator CLK(R/X); FS(R/X)P = 1, frame synchronization low effective.
2. receive/transmission control register (RCR/XCR)
(RX)PHASE = 0, single phase frame; (R/X)FRLEN1 = 11111, each 32 characters; (R/X)WDLEN1 = 0, character width 8-bit; (R/X)COMPAND = 11, the receive/transmission data uses a law pressure to expand; (R/X)DATDLY = 0, non-data delay.
3. the sampling rate has register (SRGR)
CLKGDV = 1, the receive/transmits the clock CLK(R/X) frequency is CLKS 1/2;
GSYNC = 1, exterior receive frame synchronization FSR synchronized CLKG; The CLKSP = 1, CLKS drop along produces sampling rate generator CLKG, then produces CLK(R/X); CLKSM = 1, external clock CLKS actuation sampling rate generator.
4. multichannel control register (MCR1,2)
RMCM = 0, receive the complete time slot to enable. XMCM=00, transmits the complete time slot to enable.
DMA disposition
DMA0~2 assigns in turn for the McBSP0~2 receive, DMA3~5 assigns in turn for the McBSP0~2 transmission. Concrete disposition following description:
1.DMA source address register (DMSRC)
Receives DMA DMSRC to deposit its corresponding the McBSP DRR address;
Transmits DMA DMSRC to deposit its corresponding the data buffer first address.
2.DMA destination address register (DMDST)
Receives DMA DMDST to deposit its corresponding the data buffer first address;
Transmits DMA DMDST to deposit its corresponding the McBSP DXR address.
3.DMA channel unit counter register (DMCTR)
The DMCTR value has established the DMA data buffer size, takes is 0×40, namely two data frames contain user time slot number.
4.DMA synchronization event and frame counter register (DMSFC)
DSYN[3:0]=0001, the synchronized event is McBSP0 receive event REVT0;
DBLW = 0, the individual character pattern, each item is 16 bit.
5.DMA mode of transmission control register (DMMCR)
AUTOINIT = 0, forbid the automatic initialization; The DMA0 DINM = 1, IMOD = 1, DMA buffer half-full and entire is full when has the interrupt;
DMA 1~5 DIMM=0, IMOD = X, does not have the DMA interrupt;
CTMOD = 1, DMA work in the ABU pattern;
DMA0~2 SIND=000, receives DMA to take is invariable for the source address;
DMA3~5 SIND=001, transmits DMA to take for the source address increment;
DMS = the 01, DMA source address space is the data space;
DMA0~2 DIND=000, receives DMA to take for the destination address increasing;
DMA3~5 DIND=001, transmits DMA to take is invariable for the destination address;
DMD = the 01, DMA destination address space is the data space.
Performance computation
The conference telephone request in each institute produces in the DMA interrupt service must complete to all conference’s attending user’s voice processing. Our take operating speed 100MIPS TMS320VC5410 as an example, this DSP instruction cycle’s time is 10ns, therefore may process in ST-BUS 125ms the instruction number is 125ms /10ns =12500 strip. Because all users attend the identical conference and the voice scope according to the time slot number increasing time the DSP operation process load is biggest, therefore we calculate the handling ability according to the above condition. When a supposition conference initiates, may simultaneously participate the number of users is x, then has the following inequality:
26x 254≤12500
And 254 for interrupt service public instruction periodicity, 26 for each user correspondence instruction periodicity.
Calculates by the above equation x≤471, but three McBSP links may a simultaneous working 3×32=96 user (2M the ST-BUS link) or 3×128=384 a user (8M the ST-BUS link), therefore conference telephone’s biggest number of users decided finally by McBSP, namely uses 2M when the ST-BUS link supports 96 users, uses 8M when the ST-BUS link supports 384 users.
The use assembly language code efficiency is high, the program execution speed is quick. The above algorithm DMA interrupt service uses the assembly language to realize, the practice proved that this algorithm is highly effective.
Conclusion
This article introduces has applied successfully based on the TMS320VC5410 conference telephone solution in CDMA in system MSC, on-line actual movement confirmed this plan to have large capacity and the high performance price ratio characteristic fully.
Reference:
1. TI, TMS320C54x_ DSP Functional Overview.
2. TI, TMS320VC5410 Fixed-Point Digital Signal Processor Data Manual.
3. TI, TMS320C54x DSP Reference Set Volume 5: Enhanced Peripherals.
4. TI, TMS320C54x DSP Reference Set Volume 1: CPU and Peripherals.
5. MITEL, MT9042C Multitrunk System Synchronizer.
