Abstract: This article introduced one kind based on DSP and the CPLD low power loss multi-channel data acquisition processing system. The overall system dynamic establishes a/D sampling channel by DSP and CPLD, controls 6 group 16 high accuracy A/D switch ADS7805 the start and the stop. Carries on the read and processing by DSP to the sampled data.
Key word: DSP; CPLD; Low power loss; Multi-channel data processing
Introduction
Along with electronic technology’s application and the development, the digital signal processing content is day by day complex, simultaneously, in many situations requests the overall system to have the low power loss characteristic. In order to satisfy this kind of request, the DSP chip design technique also to the low power loss, the high performance direction develops. Looking from the processing speed, the TMS320VC5502 operational capability had already achieved 600MMACS, namely each second might complete 600,000,000 times while adds the operation. Looking from the power loss, the TMS320VC5502 essence voltage only then 1.26V, the entire chip power loss also greatly reduces. This article introduced based on TMS320VC5502 and the CPLD XC95144 low power loss multi-channel data processing system.
Simulated signal input after the 50Hz trap circuit (filtration power frequency disturbance) and signal preelection frequency electric circuit. Carries on a/D transformation after the pretreatment simulated signal as the ADC analog input, finally realizes by DSP to digital signal filter processing. Unifies CPLD and the DSP technology, uses the CPLD programming the flexibility, controls 6 group ADC the starts and the stop, simplified the entire hardware circuit’s design, achieves dynamic chooses the sampling channel’s goal. After meanwhile transmits the DSP processing data PC, rear end PC using tools and so on MATLAB and VC after processing the data carries on analyzes. This article main introduction based on low power loss TMS320VC5502 and CPLD front end data acquisition and processing system.
ADS7805 synopsis
ADS7805 is one section has 16 quantification precision A/D transformation chip. Its basic composition structure approaches ADC, the sampling including 16 precisions based on the condenser network maintains gradually the electric circuit, the clock, to microprocessor’s connection and the three states of matter output. The ADS7805 highest sampling speed is 100kHz, the simulated signal input range for - the 10V~ 10V,5V single power source power supply, the biggest dissipated power is 100mW.
When ADS7805 is the 5V single power source power supply, the output data position is `1 ‘, the level value is 5V, what but DSP the chip I/O voltage uses is the 3.3V logic level, therefore, but also needs to add on the level switch chip in the ADS7805 data out-port, when design has selected 74ALVC164245, it may the 5V level switch be 3.3V, may also the 3.3V transformation be 5V.
Hardware interface circuit design
Looking from the hardware angle, DSP completes the core work which the filter operate, but overall system’s control core is CPLD, DSP is produces the control signal to 6 group A/D sampling operation by CPLD, is controlling the ADS7805 sampling trigger pip, 6 ADC multiplying and the demultiplexing, as well as 5V transfers 3.3V voltage transformation chip 74ALVC164245 the selection and so on. CPLD and the DSP clock input uses the 30MHz active crystal oscillator. CPLD, DSP, ADC and between level switch chip’s interface circuit as shown in Figure 1.
