Introduction
The sequential control logic electric circuit widely applies in the robot, the completely automatic domestic electric appliances, the industrial automation equipment and in other automated installment, it often uses the CPLD component to carry on the design with to realize.
If uses the schematic diagram input tool or the VHDL language description method directly designs the sequential control logic electric circuit, then the rated capacity is not high. This is because in the sequential control logic electric circuit contains the massive I/O signal, the control logic is these I/O signal logical combination, these I/O signal will be quoted massively in the entire control logic, but in the schematic diagram input tool’s part like logical gate and the trigger and so on input pin number will be fixed, the logical quotation will be not very flexible, simultaneously, the I/O signal’s massive quotations will make the segment to be too complex. VHDL is one kind of text design tool, is not the sequential control logic circuit design special-purpose tool, the sequential control logic program structure which compiles with it is directly in disorder, is not very direct-viewing, the programming and the debugging efficiency are not high.
Trapezoidal chart principle and characteristic
The trapezoidal chart is programmable logical controller (PLC) realizes the sequential control logic special-purpose design tool, describes the control logic with the trapezoidal chart to be direct-viewing easy to understand. The trapezoidal chart tool use is simple, the development efficiency is high, is very low to the electric circuit designer’s request, therefore, the electric circuit designer may use more energy in sequential control logic function realization with the optimization.
 Figure 1 model sequential control logic electric circuit’s trapezoidal chart |
The trapezoidal chart by two parallel vertical lines expressed separately the power line and the grounding, between these two vertical lines, with the horizontal line expression electricity ties, represents each kind the logical quantity (”ON” or “OFF”) the part electronic contact and the output executive part’s coil serially connect with the horizontal line an electrical return route. Many such return routes juxtapose in the same place, the shape are similar to the steps and ladders, constituted has realized needs the sequential control logic the trapezoidal chart.
Typical sequential control electric circuit’s trapezoidal chart as shown in Figure 1. In trapezoidal chart each return route, when all series’s electronic contact is at “ON” completely the condition, the return route is at the conducting state, the return route terminal output executive part coil is put through. For example, when X0 is “ON”, when X1 is “OFF”, functional element Y0 is put through, produces the output action. The functional element cannot many series, its electronic contact represent the logical quantity may quote repeatedly many times in the trapezoidal chart. Electric circuit’s each I/O signal may also quote repeatedly many times in the trapezoidal chart.
Trapezoidal chart - VHDL design method
If applies the trapezoidal chart law in the CPLD development, uses based on the trapezoidal chart VHDL design method, may design two kinds tool’s strong point to unify, thus enhances the order logic circuit design development the efficiency, simplified design difficulty.
The trapezoidal chart - VHDL design method’s overall mentality is, the performance history will divide into two stages: The first stage uses the trapezoidal chart to carry on the description and the design first to the order logic circuit’s logic, the second stage realizes the trapezoidal chart logical function through the VHDL language, and to logic which designs carries on the simulation debugging through the CPLD special-purpose development software.
In here, the trapezoidal chart’s function takes the order logic circuit’s logical prototype, is the VHDL language programming basis. Completes what with the trapezoidal chart is electric circuit’s logical function design, but the VHDL language procedure uses in realizing its logical function. The two cooperation based on division of labor, complements each other. And the trapezoidal chart - VHDL design method’s key lies in the trapezoidal chart the VHDL language description.
Trapezoidal chart VHDL description method
The trapezoidal chart constitutes by three kind of essential factors, namely input signal, output executive part and ties. Must use the special method in the VHDL procedure to carry on the effective description to these three essential factors.
(1) input signal Xi(i=0,1,…, M)
M input signal must, in the entity port explained that the sentence (the PORT sentence) gives to show. In the PORT sentence, each input signal may explain alone, may also measures group or a kind of input signal with a standard orientation (STD_LOGIC_VECTOR) to explain.
May stipulate when the input signal is logic “1″, its condition is “ON”; But is logic “0″ time, its condition is “OFF”. In the trapezoidal chart corresponds to the input signal Xi quotation in the VHDL procedure to Xi directly quote, but in trapezoidal chart to the quotation corresponds in the VHDL procedure to (NOT Xi) quotation.
(2) output executive part Yj(j=0,1,…, N)
N output executive part (i.e. output signal) must, in the entity port explained that the sentence (the PORT sentence) gives to show. If some output signal’s needs to quote in trapezoidal chart other positions, must establish in the PORT sentence its port pattern as “BUFFER (output and to internal feedback)”. In the PORT sentence, each output signal may explain alone, may also measures group or a kind of output signal with a standard orientation (STD_LOGIC_VECTOR) to explain.
May stipulate when the output signal is logic “1″, its condition is “ON”; But is logic “0″ time, its condition is “OFF”. In the trapezoidal chart corresponds to the output signal Yj quotation in the VHDL procedure to the Yj directly quote, but in trapezoidal chart to the quotation corresponds in the VHDL procedure to (NOT Yj) quotation.
(3) ties
In the trapezoidal chart’s ties have four kinds: The return route most left side horizontal line is the return route initial line (bus bar); Middle return route’s horizontal line is “and” the logical ties; Middle return route’s vertical line is “or” the logical ties; Right flank the return route and the output executive part connected line is an output line.
In the VHDL procedure, available “and” the logical operator “AND” replaces in the trapezoidal chart “and” the logical ties, with “either” the logical operator “OR” for the trapezoidal chart in “or” the logical ties, “<=” replaces in the trapezoidal chart with the signal evaluation operator the output line.
Thus, in the trapezoidal chart’s each electrical return route may describe very conveniently with one to the output signal assignment statement. Assignment statement’s left side is the output signal, right side is one by inputs/the output signal and with/or the operator constitution logical expression respectively.
Although may also use the IF branch sentence in the VHDL procedure to describe in trapezoidal chart various return routes the signal logical relation, but like this will cause the program structure to be very disorderly, the debugging will be very difficult, the readability will be also bad, will therefore not recommend with the IF sentence describes in the trapezoidal chart return route’s logic, but suggested that will use the logical expression to give the output signal evaluation the description method.
Regarding the trapezoidal chart in these output signal’s internal component, like the timer, the condition register, the shift register and so on, may use the part example sentence not outward to transfer the related storehouse part function to carry on the description, and states an intermediate signal in the syntagma for its output. When this kind of part has the output signal, its output signal evaluation for stated that the good intermediate signal, in the electric circuit other positions may or it take the inverse signal to this intermediate signal to carry on the quotation. Through the above each description method, may use the circuit logic prototype which the trapezoidal chart designs by a line of transformation is the VHDL procedure conveniently. When carries on the circuit logic functional design, does not need to be the VHDL procedure grammar and the program structure spends the excessively much time, can even more concentrate the circuit logic functional design and the optimization, simultaneously also causes the VHDL program logic which compiles to be clearer, the readability is better.
Application example
Following the model sequential control electric circuit’s example which through shown in Figure 1 shows the trapezoidal chart the VHDL description method.
In Figure 1, X0, X2 and X4 respectively are three output circuit’s start signal, X1, X3 and X5 respectively are three output circuit’s stop signal, Y0, Y1 and Y2 respectively are three output circuit’s output executive parts. When after Y0 start output, only then permits the Y1 start; When after Y1 start output, only then permits the Y2 start. reset is the CPLD chip on electricity reset signal, the low level is effective.
Realizes the VHDL program logic which this electric circuit controls to be as follows:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY sequence IS
PORT (X0, X1, X2, X3, X4, X5: IN STD_LOGIC;
RESET: IN STD_LOGIC;
Y0, Y1, Y2: BUFFER STD_LOGIC);
END sequence;
ARCHITECTURE ladder OF sequence IS
BEGIN
PROCESS (RESET, X0, X1, X2, X3, X4, X5)
BEGIN
IF (RESET=’0′) THEN
Y0<=’0′; Y1<=’0′; Y2<=’0′;
ELSE
Y0<= (X0 OR Y0) AND (NOT X1);
Y1<= (X2 OR Y1) AND (NOT X3) AND Y0;
Y2<= (X4 OR Y2) AND (NOT X5) AND Y1;
END IF;
END PROCESS;
END ladder;
Carries on the simulation using the MAX PLUS II simulation tool fixed time to the above procedure, result as shown in Figure 2. From the succession simulation’s result may see that electric circuit’s output logic is completely consistent with trapezoidal chart prototype’s logic.
Conclusion
This article through to a typical sequential control electric circuit trapezoidal chart’s VHDL programming and the succession simulation, indicated that the trapezoidal chart - VHDL design method is correct feasible. The trapezoidal chart’s method introduction enables the VHDL procedure the design to obtain the simplification, designs the program structure is succinct, the output logic expression is clear. The trapezoidal chart and the VHDL procedure division of labor is clear, the circuit logic functional design’s work undertakes by the trapezoidal chart, but the VHDL procedure only need be responsible to the trapezoidal chart logical function carries on describes and produces CPLD the downloading document. Thus, takes manager respectively to two kind of design tools, causes with CPLD to develop the order logical control electric circuit and system’s efficiency has the enhancement.
