Abstract: Take the infrared imagery processing system which constitutes by the ADSP-TSl01 high speed figure processor and the EPM3256 complex programmable logic component as an example, introduces in detail the system the DSP DMA channel’s application.
Key word: Infrared imagery processing; ADSP-TSlOl; DMA; CPLD
1 introduction
The infrared imagery processing system’s data volume of goods handled is big. The processing algorithm is complex. The infrared imagery processing system which constitutes by the high speed figure processor and complex programmable logical component (CPLD) is the current infrared imagery processing system’s one kind of trend of development. Extricates the high speed processor from the arduous data transmission, concentrates in is engaged in the imagery processing, solves the speed bottleneck’s important means.
The direct memory deposits and withdraws (DMA) is in CPU does not need in the situation which intervenes to carry on the data transmission automatically the way. It carries on the real-time signal processing regarding floating point DSP to have the very vital role. At the same time. In order to display the DSP core arithmetical unit the high speed operational capability. Must the first procedure and the data transmission to the DSP memory. This usually needs the DMA operation to realize; On the other hand the .DSP system must with the external signal correspondence, no matter is the data input outputs, needs DMA to complete. Will otherwise affect the DSP nucleus the high speed operational capability.
ADSP-TSlOl is new floating point DSP which AD Corporation promotes one. Its interior has the special DMA controller. Also has provided many DMA channels. Different channel correspondence different exterior uses does. This article first summarizes the introduction the infrared processing system which constitutes by ADSP TPSl01 and EPM3256 CPLD. Then carries on the detailed analysis to system’s several kind of model DMA operation.
2 system structures
This article introduced the infrared processing system mainly uses in the 320×240 picture element infrared imagery processing. Carries on the examination, the track and the recognition to the background goal. System’s hardware architecture as shown in Figure 1. This system uses 2 ADSP-TS101 to take the processor, 2 FIFO takes the input output buffer, 1 SDRAM takes the exterior memory, 1: EPM3256 CPLD takes the logical control.
Before this system’s processing is the infrared imagery gathering process. Gathers the infrared imagery data undergoes the exterior connection first to transmit in input block FIFO. When some image data transmission finished, used TSl01 the unique FLYBY transmission mode to transmit the data from input block FIFO in SDRAM, then DSP carried on processing and so on object detection to the image data. The processing result saves first in DSP RAM, finally inputs to output cushion FIFO. And includes FIFO to SDRAM, SDRAM to DSP and the DSP data transmission, because has used the DMA transmission, does not take the DSP resources, sharpened system’s handling ability greatly.
3 ADSP-TSl01 DMA descriptions
ADSP-TSl01 is TigerSharc the series DSP first member, has the extremely high operational capability. Its internal DMA controller permission takes the data transmission the backstage task execution, thus releases the processor essence. Its interior has 14 DMA channels, as shown in Figure 2, is corresponding the different type transmission operation separately. 4 channels use in the exterior memory equipment specially, 8. The DMA channel uses in the chain street intersection, but also some 2 channels use in automatically. DMA operation. The diverse transmission method causes ADSP-TSl01 to transmit the data to be convenient. Using the DMA controller, the DSP processor may carry out the following several type data transmission:
(1) internal memory to the exterior memory or between the peripheral device equipment’s data transfer which maps with the memory;
between (2) exterior memory and exterior peripheral device skip type data transmission;
(3) exterior memory to chain street intersection I/O data transmission;
(4) chain street intersection I/O to processor interior memory’s data transmission:
(5) chain street intersection I/O to exterior memory’s data transmission;
between (6) chain street intersection I/O closed loop data transmission.
The TSl01 DMA controller by the special-purpose controller nucleus, the transmitting end TCB register and the receiving end TCB register and so on constitutes. The DMA transmission’s data stream has the directivity, namely from transmitting end (source) to receiving end (goal). If the transmitting end or the receiving end are memories, then must describe through the TCB register. The TCB register is 128 bit registers, as shown in Figure 3. Including starts the information which DMA must. For example, 1 transmits TCB including the data pool address, the transmission data byte count, the address increase, the control information. If starts the DMA operation, must carry on the programming to the TCB register.
The TCB register is composed of 4 32 registers: DI register, DX register, DX register and DP register. The DI register is 32 bit index register, it contains the destination address which the transmission the source address or accepts, may aim at the memory, the external memory or the LINK mouth. The DX register has contained 1 16 bit counting value and 1 16 bit corrected value, saves separately in DX first 16 (the former) and latter 16. If two-dimensional DMA is enabled, this register contains the value represents X direction merely. For example: If must transmit 4 128 bit characters. The counting value by the establishment will be 0X10, but the corrected value and in the DP register’s operand length corresponds. If the operand length is the long character. Then the corrected value by the establishment will be 0X2. The DY register and the DX register correspond, when starts two-dimensional DMA only will then use. The DP register including the DMA all control information, divides into the control information and the DMA chain information.
in 4 system’s model DMA operations
Introduced in this article in the infrared imagery system, mainly uses following several kind of DMA to operate: Memory and external memory (memory and SDRAM data transmission), memory and data transmission, peripheral device and external memory’s between LINK mouth data transmission (FIFO and SDRAM data transmission).
DMA operations between 4.1 memories and external memory’s
The TSl01 processor has 4 special-purpose DMA channels, uses between the internal memory and the exterior memory’s data transmission. Each channel has 2 TCB the DP register, 1 to transmit TCB and 1 receive. The TCB. transmitting end uses for to actuate the data, the receiving end to use for to receive the data. DP register’s TY territory has assigned the DMA transmission type which must carry out.
Realizes the exterior memory to have 2 ways with the internal memory’s data transmission: First, carries on the programming to 4 DMA channel’s 1, moves to person another memory the block data from a memory. This time. Transmits and receives TCB to need to carry on the disposition: Second, uses in 2 AutoDMA channel’s one, this time, the peripheral device first to channel’s 2 TCB register programming, then writes the person data to the goal AutoDMA data register. Carries on to this address writes the operation, activates corresponding DMA.
Below take explains the first usage in the infrared processing system’s application as the example. If must SDRAM in the address be 0×400000~
In the Ox4003FF 1024 integers 0 transmit with the DMA channel to memory address 0xS0000~0×803FF. Available under
The programming realizes:
XR0=0×400000:← DI Register
XRl=OxO4D00004:← DX Register
XR2=0×00000000; <- DY Register
XR3=Ox87000000:←DP Register
DCS0=XR3:0:
XR8=0×80000; <- DI Rester
XR9=ox04000004; ←DX ReRister
XRl0=0×0000000; <- west DY Re sler
XRll=ox47000000; <- DP Register
DCD0=XRll:8:
4.2 memories and LINK DM_A operation between mouth
The TSl01 chain street intersection has provided fast, the independent correspondence mechanism for the processor interior or the exterior data transmission, it has provided the point-to-point means of communication for between system’s in DSP. Each DSP has 4 chain street intersections, each chain street intersection constitutes by 8 bidirectional data lines and other 3 pilot wires. Chain street intersection’s structure as shown in Figure 4. Each chain street intersection has 2 ports (transmitting end and receiving end) and 2 buffers. The buffer uses in packing or the bale breaking chain street intersection data, carries on the data exchange with the internal memory.
The TSl01 4 chain street intersection may use the DMA way transmission or the receive data, may realize the chain street intersection and the internal memory, the exterior memory or between other chain street intersection bidirectional data transfer. The processor has provided 2 special-purpose DMA channels for each chain street intersection, 1 uses in transmitting the data, 1 uses in receiving the data. Two DMA channels may with the internal or the exterior memory interface. When the receiving end register is spatial, and the link DMA channel enables time, the chain street intersection to transmits the DMA channel to send out DMA to request that the link 1:3 may continue to the buffer area to write the data. When receives the register to be full, and the DMA channel enables time, the chain street intersection to receives the DMA channel to send out the DMA request.
Take the infrared processing system’s in application as an example, like chart l shows .DSPO to pass the LINK mouth 0 and the DSPl LINK mouth 1 connected. If the N integer transmits orally DSP0 in memory array data_tx through the link loses to DSPl in the memory in array data_rx. Must first channel carry on the programming to DSPl LINK the mouth l receive DMA, then channel carries on the programming to DSP0 LINK the mouth O transmission DMA.
In DSPl procedure:
TCB_temp.DI=data_rx;
TCB_temp.DX=4 I(N<<16);
TCB_temp.DY=O:
TCB_temp.DP=0×47000000;
q=_buihin_compose_128 ((1ong long) TCB_temp.DI │
(10ng long) TCB_temp.DX<<32. (10ng ions)
(TCB_temp.DY│ (10ng long) TCB_temp.DP<<321);
builtin_sysreg_write(LCTLl.0×000004D2); // hypothesis
Chain street intersection control register
builtin_sysreg_write4 (DC9, cO;
In DSPO procedure:
TCB_temp.DI:data_tx;
TCB_temp.DX=4 I(N<<16);
TCB_temp.DY=0:
TCB_temp.DP=0×47000000;
q= builtin_eompose_128 ((10ng long) TCB_temp.DI │
(10ng long) TCB_temp.DX<<32, (1ong 1ong)
(TCB_temp.DY I (1ong long) TCB_temp.DP<<32));
buihin_sysreg_write(LCTL0,0×000004D2);
/, establishes the chain street intersection the control register
builtin_sysreg_write4(DC4, q);
In the above programming, disposes the chain street intersection clock 1/3 nuclear clock. When processor nucleus work in 300 MHz and chain street intersection work when 100 MHz the chain street intersection’s turnover rate may achieve 200 MB.
4.3 external memory and peripheral device DMA operations (leap transmission)
In the programming, must realize the exterior memory’s with other external instrumentation between data transmission, usually needs through the processor essence the data transmission to the processor. In this case the .TSl01 processor supports the brand-new data transmission is the leap passes on (continued from the 60th page) the losing side type. This time does not need to carry on visit to the internal memory, the data directly and exterior between other equipment transmits in the exterior memory. Under leap transmission mode. May regard as TSl01 the independent DMA controller. The leap transmission mode and the standard DMA transmission mode is similar, programming also basic same, but the data width must with the exterior 10 equipment match. Moreover can only use the DMA channel 0.
5 concluding remark
Using the DSP DMA function is the solution high speed image processor speed bottleneck’s important means fully. A ADSP TS101 DMA operating function is formidable, various. It may not complete the image data while signal of stop processor algorithm handle work the transmission, enhances processing system’s performance. This article analyzes several kind of operations obtain the concrete practice in the infrared imagery processing system, obtains the good effect.
