1. introduction
Along with the large scale integrated circuit and monolithic integrated circuit’s rapidly expand, the complex programmable logical component (CPLD) has the use to be nimble, the reliability is high, the function formidable merit, obtained the widespread application in the electronic products design. CPLD may realize in the system programs, redundant many times, moreover also the compatible IEEE1149.1(JTAG) standard’s test drive end and boundary scan ability, uses the CPLD component to carry on the development, not only may enhance system’s integrated degree, the reliability and the extendibility, moreover reduces product greatly the design cycle. Because CPLD uses connects the structure continuously, easy to forecast the time delay, thus causes the circuit simulation to be more accurate. CPLD is the standard large scale integrated circuit product, may use in each kind of digital logic system’s design. In recent years, along with used the advanced integrated craft and the production in enormous quantities, the CPLD component cost drops unceasingly, the integration density, the speed and the performance large scale enhanced, this kind of chip might realize a complex digital circuit system; In addition easy to operate’s development kit, brings for the design revision is very greatly convenient. This article take Xilinx Corporation’s CoolRunner the series CPLD chip as an example, realizes under adding water explodes when shock-wave signal data record.
2 submarine shock-wave recording instrument’s composition and principle of work
2.1 function introductions
This submarine shock-wave recording instrument electric circuit mainly uses in tests when the subsurface burst the shock-wave strong and the weak, it can the shock-wave signal data which gathers carry on the profile reproduction through the private data processing software, and may read out the shock-wave from the profile the pressure peak value and the rising time and the response time.
2.2 architecture composition
The submarine shock-wave recording instrument by the data recorder, the connection, the test data processing software three parts is composed. The data recorder is a collection pressure transmitter, the transient waveform recorder, the connection, the power source was equal to that a body’s miniature testing device, the built-in voltage amplifier, the direct-current power supply, the input signal after the enlargement, high speed A/D transforms realizes the automatic digital storage.
2.3 principles of work
Pressure transmitter’s leading role is the sensitive submarine shock-wave strong and the weak, its output through constant current electric circuit impact pressure signal conversion for voltage signal. Recuperates the electric circuit the signal conversion after the modulus switch’s simulation quantity input range, carries on gathering by the modulus switch to it, after transforming the digital signal peak-to-peak value carries on the judgment through the center control module and carries on the initialization, the recursion to the memory address, the digital signal namely is saved. When reading the computer sends out the reading clock and the order through and the mouth, will enter to three groups memories travels chooses, to select patches or strips of land as worth saving for seed and data read-out.
The recording instrument triggering plan uses negative detention internal trigger: When the signal peak-to-peak value is bigger than or was equal to sensor output full scale when 10% starts negative detention, but when the signal peak-to-peak value is smaller than this value the system is at the circulation gathering condition, thus may the interference protection cause effectively harms triggering with not to trigger and accurate, records the entire shock-wave profile completely. The submarine shock-wave recording instrument’s principle composition diagram see Figure 1.
Figure 1 submarine shock-wave recording instrument work schematic diagram
3 CPLD applications
Mainly uses CoolRuner which in this design Xilinx Corporation develops the CPLD chip to complete the design. What this article designs uses is this series XCR3256 component, may realize 6000 digital logic electric circuit, in inlays 256 great units, supports 4 overall situation clocks, has the low power loss, to be possible fast ISP, the time delay to be possible to forecast and so on characteristics. We select the XCR3256 chip to realize the submarine shock-wave recording instrument master control module, this master control module uses to various periphery component’s control, is coordinated various periphery component the work. The periphery component mainly has the power source chip set, the static RAM memory, the crystal oscillator, a/D switch, LED, and the mouth and so on. And the crystal oscillator including produces master clock’s 12MHz crystal oscillator and produces the time delay counting clock’s 1MHz crystal oscillator. The master control module with various periphery component’s diagram as shown in Figure 2.
Figure 2 submarine shock-wave recording instrument master control module and various periphery component circuitry diagram
3.1 flexible, the development cycle is short
Figure 2 A/D switch uses AD7470. Its start transformation input end CONVST by the master clock frequency division obtains, and the sampling frequency is programmable. The programmable delay circuit is dials the code switch through four groups to input the different level combination to CPLD to realize, through establishes CPLD the digital logic pair process time delay counting clock’s 1MHz crystal oscillator counting, inputs the different level combination, thus decodes has the different delay time, but changes the level combination only to recording instrument’s kneading board operation then. The CPLD component matches by the ISE development system may complete the design input, the translation, the confirmation and the programming, the design verification may carry on the complete simulation, in worst situation timing analysis and function testing. The designers do not need the programmer to be possible to restructure the number system, has “the hardware does softly” characteristic.
3.2 power losses are low, the integration rate is high
Figure in 2 power source management electric circuit’s power source chip mainly includes MAX1658, MAX1659 and MAX1616, their common ground has a SHDN input end, when SHDN end for low level, regardless of the voltage input end input great voltage, the output voltage is 0V, but only then, when the SHDN end is the high level, when input end turning on appropriate voltage, the out-port can have the corresponding voltage value to supply the system normal work. Because installs works finally in submarine, needs the battery power supply, this requests the electric circuit to lower the power loss.
The recording instrument works when altogether has 5 conditions: The low power loss time delay establishment waits the electricity condition, the low power loss to treat the triggering condition, the data record condition, the data maintains the condition, the readout condition. The condition transformation is completes under the center control module control. The system has brought a data maintains a power source, therefore does not use the system to be at the data maintains the condition. After master control module electricity, dialed the code switch establishment delay time through four groups, the delay time after on the other module automatic electricity, was at treats the triggering condition, prepared to carry on gathering to the data. Along with trigger pip’s arrival, the system mode is transformed to the data record condition, after the record finished, the system enters the low power loss data maintains the condition waited for that is recycled. After recaption installment, when reading the system conversion for the readout condition, after the reading had ended, the system is at the data maintains the condition, the waiting next record. Such system records every time one time, its correspondence’s condition must circulate one time. In the system work’s different period, we may control each power source chip through the CPLD interior digital logic the SHDN input end, lets the chip SHDN input end which must work set high, does not need to work the chip SHDN input end sets lowly, thus has realized the low power loss.
The Xilinx component’s integration rate scope may reach 300~250000 available gates, may integrate the existing logical function very easily, regardless of these logic are by many discrete logic components, many PLD perhaps FPGA is composed, the component which has custom-made by several composes. In the system design, the integration rate enhancement means that the equipment scale reduces, primary device quantity reduces, but primary device quantity reduces on the necessity reduces the power loss, specially the embedded array block (EAB) use, may integrate the memory in the CPLD chip, is specially advantageous on the chip the systematic design, reduced system’s cost, the equipment power loss, moreover can enhance system’s performance and the reliability.
3.3 low costs, redundant reliability
Uses the CPLD component to carry on the circuit design, may reduce the board large scale the area, the spot and the connector, reduces the assembly and the debugging expense. The massive separation component when carries on the board light display, often will occur as a result of the faulty soldered joint or the bad contact creates the breakdown, and this kind of breakdown discovered with difficulty frequently, will bring the enormous difficulty for the debugging and the service. Therefore, after using the CPLD component, because the integration rate enhances, primary device quantity reduces, board quantity reduces, thus the extension telephone combination reduces, reduces equipment’s comprehensive cost, causes equipment’s reliability to enhance greatly.
4 design processes
Xilinx Corporation’s CPLD development kit ISE, supports many kinds of input modes, has provided enormous convenient to the design development, therefore this system uses ISE to carry on the design. It may complete the design input, the edition, with the verification tool connection conveniently, the designers may use the standard the EDA design input tool to establish the logical design, uses the ISE compiler to carry on the translation for the XCR3256 component, its design cycle like chart 3.
4.1 design inputs
The design input mode has the schematic diagram input, the hardware describes the (HDL) language input, the profile input and so on many kinds of ways. Recording instrument electric circuit’s each function block: The one-way bus buffer’s production, a/D clock signal, writes a letter the number and selects patches or strips of land as worth saving for seed the signal the production, the address generator production, reads, writes the order and the data transmission control, disappears to the reading clock shakes and so on is uses hardware description language (VHDL) to realize, finally uses the schematic diagram input each function block to connect in together. Uses the language description the merit is the efficiency is high, the result easy simulation, the signal observation to be also convenient.
4.2 design processing
Reads the information separately in the design document and produces the programming document and the simulation document and the automatic error locating, the design rule inspection as well as various components division, the compiler can also realize the request which fixed time the user assigns, for example: Dissemination time delay (tPD), clock rate (f osc) and so on.
Figure 3 design cycle
4.3 design simulations
After designing completes, the designer may through the simulation confirm designa circuit’s characteristic whether with design goal consistent, here is tests in the logical function and the component worst situation through the timing simulation the time relationship. May observe the result very intuitively through the simulation result whether to meet the design requirements.
4.4 component programming
After completing the design input and the succession simulation operation, last step is carries on the programming to the XCR3256 component, carries on the disposition with the computer through the Xilinx special-purpose programming electric cable, the translation production configuration files parallel passes after the computer receives on unguardedly the Xilinx special-purpose programming electric cable, receives component’s programming connection again, provides the programming software using the ISE development system then to carry on the disposition to the component. This method’s merit is the disposition is convenient, is rapid, is advantageous for the revision. This is advantageous to electric circuit’s debugging, the electric circuit debugs when needs to divide frequently to the circuit design debugs gradually. Through the change design, may program to the component, easy to complete the electric circuit debugging.
5 concluding remark
In this article introduced the shock-wave strong and the weak which the submarine shock-wave recording instrument mainly uses in tests when the subsurface burst to produce, uses the CPLD component to carry on the design, enhanced the system design flexibility greatly, enhanced system’s reliability and the integration rate, reduced the product development cycle, meanwhile may reduce the designed cost, saves the PCB board the area and the wiring difficulty, enhanced the equipment reliability, obtained the satisfactory test result.
Reference:
1. Wang Bo. CPLD in circuit wafer failure diagnosis application. The micro computer information .2002 year 3rd issue: 43~44
2. Song Wanjie, Luo abundant, Wu Shunjun writes. CPLD technology and application. Xi’an Electron Branch Technology University Publishing house, 1999
3. Chen Guang dream. Programmable logical component’s principle and application. Shanghai: Fudan University publishing house, 1997
4. Xu Zhijun, Xu Guanghui. CPLD/FPGA development and application. Beijing: Electronics industry publishing house, 2002
