Abstract: Embedded system’s low power loss design needs the overall analysis various aspects factor, the master plan. At the beginning of the design, each factor often is restricts, the mutual influence mutually, will reduce the system power loss the measure sometimes to bring other aspects “negative effect”. Therefore, reduces the system overall power loss, needs to analyze and the computation carefully. This article designs two aspects from the hardware and the application software, elaborated take monolithic integrated circuit as when core embedded system low power loss design must consider some questions.
Key word: The low power loss design hardware design application software designs the low power loss pattern
In the embedded application, system’s power loss is valued people’s more and more, this point regarding needs the battery power supply the portable system to be especially obvious. Reduces the system power loss, lengthens battery’s life, reduces system’s run cost. Regarding take the monolithic integrated circuit as the core embedded application, the system power loss’s minimum needs to design two aspects from the software and hardware to obtain.
Has used the real-time operating system along with more and more embedded applications, how to reduce the system power loss in the operating system stratification plane also to become one to be worth the matter of concern. As space is limited, this article only designs two aspects from the hardware design and the application software to discuss.
1 hardware design
Selects has the low power loss characteristic monolithic integrated circuit to be possible to reduce the system power loss greatly. May from the power line voltage, the monolithic integrated circuit internal structure design, the system clock design and the low power loss pattern and so on several aspects inspects a model of monolithic integrated circuit’s low power loss characteristic.
1.1 select as far as possible simple CPU essence
When chooses the CPU essence prohibited that pursues the performance constantly. 8 machine are sufficient, is not unnecessary to select 16 machine, the choice principle should be “sufficient good”. Now monolithic integrated circuit’s running rate is getting quicker and quicker, but the performance promotion often brings the power loss increase. A complex CPU integration rate is high, function, but the internal transistor are many, always leaks the electric current to be big, even if enters the STOP condition, leaks the electric current also becomes noticeable; But the simple CPU essence power loss is not only low, the cost is also low.
1.2 choice low voltage power supply system
Reduces monolithic integrated circuit’s power line voltage to be possible to reduce its power loss effectively. Presently, the monolithic integrated circuit from reduces with the TTL compatible 5 V power supplies to 3.3 V, 3 V, 2 V and even 1.8 V power supplies. The power line voltage descends fall, must give credit the semiconductor craft development. From the original 3 μm crafts to the present 0.25, 0.18, 0.13 μm craft, the CMOS electric circuit’s threshold level threshold value reduces unceasingly. The low voltage power supply may reduce system’s operating current greatly, but because transistor’s size reduces unceasingly, the pipe leaks the electric current to have the enlargement tendency, this is also to reduces a power loss disadvantageous aspect.
At present, monolithic integrated circuit system’s supply voltage still by 5 V primarily, but in the past 5 years, 3 V power supply’s monolithic integrated circuit system quantities increased 1 time, 2 V power supply’s systems unceasingly are also increasing. Will cross again for five years, low voltage power supply monolithic integrated circuit quantity will possibly surpass 5 V voltage power supplies the monolithic integrated circuit. So looks like, the power line voltage will reduce will be an important tendency which the future monolithic integrated circuit will develop.
1.3 choices have the low power loss pattern system
What the low power loss pattern refers to is the systematic waiting and the stop pattern. Will be under this kind of pattern the monolithic integrated circuit power loss will be smaller than under the movement pattern power loss greatly. In the past the traditional monolithic integrated circuit, in moved under the pattern to have wait and the stop two instructions, might cause the monolithic integrated circuit to enter the waiting or the stopped state, achieved the province electricity the goal.
Waits for under the pattern, CPU stop work, but the system clock does not stop, monolithic integrated circuit’s periphery I/O module does not stop the work; The system power loss reduces generally limitedly, is equal in the working pattern 50%~70%.
Stops under the pattern, the system clock will also stop, interrupts by the external event starts the clock system clock, then awakens CPU to continue to work, the CPU current sinking may fall to μThe level. In stops under the pattern, CPU itself in fact already did not consume any electric current, if wants to further reduce the system power loss, must switch off as far as possible monolithic integrated circuit’s each I/O module. Along with the I/O module’s closure one by one, system’s power loss getting smaller, enters the stop pattern the depth to be also getting deeper and deeper. Enters the depth stop pattern to be no different with the close-down, by now monolithic integrated circuit consumed the electricity to be possible to be smaller than 20 nA. And what must prompt specially, after internal RAM stop power supply, in RAM saves the data will lose, i.e., after awakening CPU, must make the initialization again to the system. Therefore before letting the system enter the depth stopped state, must the important system parameters preservation in the nonvolatile storage, like in EEPROM. The depth stop pattern has switched off all I/O, possible to awaken the way to be very also limited, generally can only be the replacement or the IRQ interrupt and so on.
The retention I/O module are more, the system permission awakens the interrupt source to be also more. Monolithic integrated circuit’s power loss will awaken the way according to the retention the difference, drops to 1μA to several dozens μA between. For example, the user may retain the exterior keyboard interrupt, the retention asynchronous serial port (SCI) receives the data interrupt and so on to awaken CPU. The retention awakens the way to be more, the system consumes the electricity also to be able many somewhat. Other possible to awaken the way also to have the solid clock to awaken, the watch-dog to awaken and so on. In the stopped state shallow situation, the exterior crystal oscillator electric circuit works.
Figure 1 take the Freescale HCS08 monolithic integrated circuit as an example, gives under the different movement pattern the system power loss. HCS08 is 8 monolithic integrated circuits, has many series, each series I/O module number differs from, but under the low power loss pattern’s current consumption is approximately same.
Under chart 1HCS08 monolithic integrated circuit various patterns consumes the electricity
Take R series monolithic integrated circuit as the example: In the room temperature (25℃), including the I/O mouth’s load, take 2 V power supplies, does not suppose the programmable phase-locked loop clock as 16 MHz (main line clock 8 MHz), the typical magnitude of current is 2.6 mA, when temperature increment to 85℃, the supply current also elevates to 3.6 mA; But uses 3 V power supplies, this group of data elevate to 3.8 mA and 4.8 mA. With 2 V power supplies, when uses exterior crystal oscillator 2 MHz directly (main line clock 1 MHz), the model running current drops to 450 μA. Under waiting status, because the clock has not stopped, consuming the electricity situation and the clock rate has the very big relations, the economical power loss is limited; But enters the mild stop (stop3), awakens by the external interrupt, current consumption in 0. 5 μA about. In the moderate stop condition (stop2), the power loss may further reduce. Uses internal 1 kHz the clock, maintains 1 movement the clock, the periodicity awakens CPU, increases the electric current approximately is 0.3 μA. In the depth stop condition (stop1), the RAM data also no longer retains, can only restart the system through the external reset, this time’s current consumption may fall to 20 nA. The above data is surveys under the room temperature obtained. When the ambient temperature elevates to 85℃, the current consumption possibly increases 3~5 times.
1.4 choice appropriate clock plan
Clock’s choice is quite sensitive regarding the system power loss, the designer needs to pay attention to two aspects the questions:
First is the system bus frequency must be as far as possible low. The monolithic integrated circuit internal joint current consumption may divide into two part of - - running currents and leak the electric current. Ideal CMOS switching circuit, when maintains the output state is invariable, consumed power. For example, the typical CMOS phase reverser electric circuit, as shown in Figure 2, when the input end is a zero hour, the out-port is the 1, P transistor breakover, the N transistor closure, does not have the electric current to wind through. But in fact, because the N transistor existence leaks certainly the electric current, and enhances along with the integration rate, manages the base to be thinner, the leakage is inoperable for lack enlarges. Temperature increment, the CMOS turn over threshold voltage will reduce, but will leak the electric current along with the ambient temperature markup fill-out. When the monolithic integrated circuit moves, the switching circuit legal reason for judgment “1″ does not change “0″, by “0″ changes “1″, the consumption power is causes by the monolithic integrated circuit movement, we call it “the running current”. As shown in Figure 2, when two transistors transform the breakover, the closure condition mutually, because two pipe’s switch delay times are impossible completely consistently, while some flash will have two pipes the breakover situation, this time the power source will arrive between will have instantaneous big electric current, this will be the monolithic integrated circuit running current important source. May see, the running current is nearly and monolithic integrated circuit’s clock rate is proportional, therefore cuts system clock’s movement frequency to be possible as far as possible to reduce the system power loss effectively.
Figure 2 model CMOS phase reverser
Second is the clock plan, is also whether to use the phase-locked loop, to use exterior questions and so on crystal oscillator or internal crystal oscillator. New generation’s monolithic integrated circuit, if flies thinks of Cull’s HCS08 series monolithic integrated circuit, internal has the internal crystal oscillator, may take the clock source directly. Uses the internal crystal oscillator the merit is may save outside the peel off the crystal oscillator, reduces system’s hardware cost; The shortcoming is the internal crystal oscillator precision not high (error generally about 25%, even if after calibrating, also possibly has 2% relative errors), will increase system’s power loss.
The modern monolithic integrated circuit uses the phase-locked loop technology generally, causes monolithic integrated circuit’s clock rate to be possible by the programmed control. The phase-locked loop permission user outside the piece the frequency of use low crystal oscillator, may reduce the platelet level noise very greatly; Moreover, as a result of the clock rate may by the programmed control, the system clock be possible to adjust in a very wide scope, the main line frequency often can rise very much high. But, the use phase-locked loop will also bring the extra power dissipation.
The list says on the clock plan, uses the exterior crystal oscillator, and does not use the phase-locked loop is the power dissipation smallest one kind.
2 application software aspect consideration
The reason that use “application software” the view, is to differentiate in “the system software” or “the real-time operating system”. The software is neglected frequently regarding a low power loss system’s importance by the people. An important reason is, on software’s flaw does not look like the hardware to be such easy to discover, simultaneously also does not have a strict standard to judge a software’s low power loss characteristic. For all this, the designer must as far as possible the application low power loss characteristic reflection in the software, avoid these “cannot see” the power loss loss.
2.1 use “the interrupt” to replace “the inquiry”
A procedure use interrupt mode inquires the way regarding some simple applications not that important, but is actually very different in its low power loss characteristic. The use interrupt mode, CPU may anything not do, even may enter the waiting pattern or the stop pattern; But inquires under the way, CPU must not stop visits the I/O register, this will bring the extra power loss.
2.2 use “great” to replace “the subroutine”
The programmer must be clear, reads RAM compared to read Flash to bring a bigger power loss. Is precisely because of so, low power loss performance prominent ARM only permits a second son procedure transfer in the CPU design. Because CPU enters time the subroutine, first will thrust the current CPU register the storehouse (RAM), when departure will spring the CPU register the storehouse, will bring like this at least two times to the RAM operation. Therefore, the programmer may consider that replaces the subroutine call with the great definition. Regarding the programmer, transfers a sub-procedure is great does not have in the procedure mode of writing what differently, but great in the translation time will launch, CPU only will be the order executive order, has avoided the transfer subroutine. The only question as if is code quantity increase. At present, monolithic integrated circuit’s internal Flash is getting bigger and bigger, does not care about the procedure code quantity big some applications regarding some, this procedure will reduce system’s power loss without doubt.
2.3 reduce CPU as far as possible the operand
Reduces the CPU operation the work to be possible to obtain from many aspects: Some operation’s result was considered in advance well, places in Flash, with the table look-up method substitution real-time computation, reduces CPU the operation work load, may reduce CPU the power loss (many monolithic integrated circuits to have fast effective look-up instruction and addressing system effectively, with optimizes table look-up algorithm); The inevitable real-time computation, calculated that sufficed to the precision to finish, avoided “excessively” the computation; The use short data type, for example, uses the character 8 bit data to substitute 16 trueing data as far as possible as far as possible, uses the score operation to avoid the floating number operation as far as possible and so on.
2.4 let the I/O module batch operation
Does not use the I/O module or the intermittent use’s I/O module needs to switch off promptly, saves the electrical energy. The RS232 actuation needs the suitable power, may use a monolithic integrated circuit’s I/O pin to control, when does not need to correspond, will actuate to switch off. Does not use the I/O pin must establish the output or establish the input, with pulls the resistance to pull high. If because the pin does not have the initialization, possibly will increase the monolithic integrated circuit to leak the electric current. Must pay attention to some simple seals specially the monolithic integrated circuit not to direct the individual I/O pin, cannot see the I/O pin to these not to forget the initialization.
3 conclusions
A successful low power loss design should be the hardware design and the software design union. Starts from the hardware design, should realize a low power loss application fully the characteristic, chooses a model of appropriate monolithic integrated circuit, through to its characteristic understanding, design system plan; In the software design, must consider the low power loss programming the particularity, and uses monolithic integrated circuit’s low power loss pattern as far as possible.
As space is limited, discussed in low power loss design some frequently asked questions merely, more questions only could depend on the designer to go to the reality to analyze and to solve.
