VirtexTM-5 serial products’s extrusion, enables Xilinx Corporation to become again to the FPGA customer provides new technical and ability leading force. Has the transition to 65 nanometer craft’s FPGA uses the traditional superiority which the light-sized craft brings: Low cost, high performance and stronger logic capability. Although these superiority can bring the exciting opportunity for the high-level system design, but 65 nanometer craft nodes itself have also brought the new challenge.
For example, when chooses FPGA for the product, the power loss consideration becomes more and more important. The very possible next generation design meeting to need in the power loss budget invariable (or smaller) in the situation, integrates more characteristics and realizes a higher performance.
In this paper, I will analyze the advantage which the power loss reduces brings. Also will introduce in many kinds of technical which and the structure innovation in the Virtex-5 component uses, they can provide the power loss lowest solution, and will not have any discount in the performance.
Reduces the power loss the advantage
The low power loss’s FPGA design brings the superiority is not only can satisfy the component work the radiation request. Although satisfies the part target is very important regarding the performance and the reliability, but how to realize this point has the huge influence regarding the system cost and the complexity.
First, reduces FPGA the power loss to enable you to use a cheaper power source, such power source uses part quantity are few, and takes the PCB area is also small. The high performance electrical power system’s cost usually is each tile 0.5 to 1 US dollar. Low power loss’s FPGA reduced system’s overall cost directly.
Next, because the power loss is directly related with the radiation, the low power loss enables you to use is simpler, a cheaper quantity of heat to manage the solution. In many situations, the designer will need no longer the radiator, or only needs to be smaller, a cheaper radiator.
Finally, because the low power loss work means less parts and the lower component temperature, will therefore enhance overall system’s reliability. The component operating temperature reduces every time 10℃, quite enhanced two times in the component life, therefore speaking of needs the redundant reliable system, the control power loss and the temperature are very important.
Power loss: Challenge and solution
FPGA (or any semiconductor device) of total power loss is equal to sum of the static power loss and the dynamic power loss. The static power loss mainly causes by transistor’s leakage current, namely transistor, even if is shut off in logic time, from source “divulging” to drain electrode or through grid oxygen “divulging” undercurrent. The dynamic power loss is the component core or I/O the energy which consumes in the switching process, is related with the frequency.
Chart 1:85℃ time static power loss comparison
Static power loss
When reduces the transistor size (e.g., from 90 nanometers to 65 nanometers), the leakage current will increase. The new craft point uses the short ditch length and the thin grid oxygen makes the electric current to be easier from transistor’s trench area or through grid oxygen divulging.
In 90 nanometer Virtex-4 serial products, Xilinx Corporation has used “three electronics grid oxide layers” the processing technology, has provided one kind of powerful impediment leakage tool to the Xilinx electric circuit designer. In first several generation of FPGA, uses two kind of grid oxygen thickness: The thin grid oxygen uses in the FPGA core the high performance, the low working voltage transistor, but the thick grid oxygen uses in the I/O module the size being big, needs to withstand the great voltage the transistor. , “Three electronics grid oxide layers” refers to simply increases one kind of middle thickness grid oxygen the transistor, its leakage must be much smaller than the thin grid oxygen’s core transistor.
“middle grid oxygen” the crystal is effective, in the component core periphery non-essential performance’s electric circuit (establishes memory likely) or does not need to carry on the split-second-selection response to the change grid-voltage the electric circuit (to transmit gate likely). The thin grid oxygen, leaks the biggest transistor only to retain is needing the split-second-selection speed the way part. Finally, the total component leakage is reduced greatly, simultaneously the performance still could have the very big enhancement compared to previous generation FPGA.
Three electronics grid oxide layer craft caused the Virtex-4 component to compare competitive 90 nanometer FPGA to reduce equally in the static power loss has surpassed 70%. This result is successful, therefore in the Virtex-5 serial products has used this technology massively, reduces the leakage on 65 nanometer craft points.
Although the field forecast that 65 nanometer component’s static power losses will have the large scale enhancement, but Figure 1 had demonstrated three electronics grid oxide layer craft caused 65 nanometer Virtex components (to be highest at worst temperature) the working condition to issue with the size suitable 90 nanometer Virtex-4 component same level static power loss. Therefore, the Virtex-5 serial products and the competitive high performance FPGA product compares, has the true superiority in the static power loss aspect.
Dynamic power loss
The dynamic power loss is 65 nanometer FPGA brings some other aspects the challenge. The dynamic power loss’s formula is:
Dynamic power loss = CV2f
And C is time the point switch’s electric capacity; Vth, the supply voltage, f is the turn-on frequency. 65 nanometer craft nodes caused FPGA the logic capability and the performance had the remarkable enhancement compared to the traditional component, i.e. more point work in a higher frequency. If other aspect’s condition is invariable, the dynamic power loss will increase.
But, speaking of 65 nanometer craft node’s dynamic power loss, also has a good news: The FPGA core’s supply voltage (V) and the point electric capacity (C) usually can drop in each generation of new craft, thus causes the dynamic power loss to drop compared to previous generation FPGA.
In the Virtex-5 component, the core supply voltage (VCCINT) 1.2V which uses from Virtex-4 drops to 1.0V. Because the parasitic capacity changes small (with a smaller transistor related), as well as the logical block’s on-line length mutually shortens, the electric capacity changes is small, causes the point electric capacity to reduce. In addition, the Virtex-5 component has used one kind of coefficient of dielectrical loss low material between the metal interconnection level.
The Virtex-5 component’s average point electric capacity probably reduced 15% compared to the Virtex-4 component. In addition stepping down of voltage brings the advantage, to little was equal in reduced the Virtex-5 component’s core dynamic power loss 35-40%.
Besides “the craft minification” brings to 65 nanometers institutes the inherent 35-40% dynamic power losses reduce, Virtex-5 component’s construction innovation, but can also further reduce each design the power loss. Majority may increase the dynamic power loss some point electric capacity, is causes by the logical function interconnection line. The new Virtex-5 construction fundamentally reduced the segment electric capacity in two aspects:
Virtex-5 may dispose the logic module (CLB) is based on 6 input search table (6-LUT) the logical organization, is uses in the beforehand component 4 inputs the search table. This means that can realize more logic in each LUT, quite Yu Jiaoshao logical level, thus reduced to the logical function between the big electric capacity segment demand.
The Virtex-5 interconnection structure has included the diagonal line symmetrical segment at present, means that each CLB and all neighboring modules (including are in diagonal line position module) between to have directly “sole” the connection. When between the logical function needs to connect, this connection has the possibility to become the total capacitance slightly “sole” the connection, but the former interconnection structure will possibly need two or more points regarding the same connection question.
Figure 2: Counter modular design dynamic power loss comparison
the 6-LUT structure and the improvement interconnection pattern, through reduces the average point electric capacity to reduce the core the dynamic power loss, the effect goes far beyond only uses the improvement which 65 nanometers crafts bring. Figure 2 had demonstrated from modular design core dynamic power loss measurement result, in each Virtex-5 component and the Virtex-4 component has 1024 8 counters. These actual measurement result showed that in the craft and the structure common optimization brings the dynamic power loss reduced has surpassed 50%.
Hard IP module
In the Virtex-5 component contains the hard IP module (uses for realizes some commonly used function electric circuit quantity specially), surpasses field other any section of FPGA. Compares the use general FPGA logic saying that the use embarks these modules the FPGA design to realize these functions, may further reduce the power loss.
Is different with the FPGA structure, in these special-purpose modules only then realizes the function essential transistor which requests. And does not have the programmable interconnection, therefore interconnects the electric capacity to be smallest. The few transistors and the small point electric capacity can reduce the static state and the dynamic power loss. Thus causes these special-purpose modules while to realize same function, the power loss only then uses the general FPGA structure 1/10.
Besides increases the new special-purpose module, in the Virtex-4 component fuses many modules, in the Virtex-5 component by the redesign, are increased the new characteristic, enhances the performance, reduces the power loss. For example, in the Virtex-4 series 18-Kb block the RAM memory is increased in the Virtex-5 component 36-Kb; Each block RAM can divide into two independent 18-Kb the memories, so that downward compatible Virtex-4 design.
What is interesting, looking from the power loss angle, each 18-Kb submodule by two 9-Kb physics memory array constitutions. Regarding majority block the RAM disposition, any regarding the block RAM read-write requested that one time only needs to visit in 9-Kb physics memory’s one. Therefore other 9-Kb memory can when is not visited by effectively “shutdown”. In brings the transition to 65 nanometers crafts the power loss reduces in the foundation, this kind of structure caused the power loss to further reduce 50%. This regarding the 9-kB module “the pingpong” the visit is new block the RAM structure inherent, this means that uses this function not to need the user or the software carries on the control. It could dynamic and carries on automatically, causes to use block RAM the design to reduce the massive power losses, and will not affect the module the performance.
The Virtex-5 component specialized middle school uses the DSP part has also made the massive improvements, realizes more functions, enhances the performance, and reduces the power loss. In the piece and in the piece comparison, new Virtex-5 the DSP piece’s power loss piece’s power loss reduced compared to Virtex-4 the DSP about 40%. This mainly gives credit to 65 nanometers crafts which discusses in front the voltage and electric capacity’s reduction.
However, because Virtex-5 the DSP piece has a stronger function and a more widespread connection, many DSP operations through used these additional the function to further reduce the power loss. In many situations, when uses the new DSP piece the complete function, the total power loss is highest may reduce 75%. Please remember, even if you are not in design a DSP product, can also use the DSP piece to realize the standard logical function (counter, accumulator, barrel type shifter), like this compared to will realize the similar function in the standard FPGA logic to save the power loss.
Finally the introduction process improvement’s special-purpose module is Virtex-5 the series LXT platform, including several lucky serial transceivers, can reach as high as 3.125Gbps the speed work. These “SERDES” module when realization has considered the low power loss demand emphatically. Each Virtex-5 in the LXT component’s full-duplex transceiver is smaller than 100 milliwatts under the 3.125Gbps speed’s total power loss, compared with the Virtex-4 serial transceiver reduced about 75%.
Figure 3: In model design existing FPGA power loss comparison
Conclusion
The Xilinx Corporation glorious innovation history can trace more than 20 years ago the first FPGA invention. Therefore Xilinx Corporation will become first to reduce the power loss naturally in the deep submicron technology to take the most important task the company. Is the same with the Virtex-4 serial products, the Virtex-5 component has also used on a series of crafts and the construction innovation, makes every effort while to provide as far as possible low power loss, still caused the performance to enhance 30% or to be more.
As shown in Figure 3, Virtex-5 serial products static power loss and Virtex-4 component quite, but has the obvious superiority compared to competitive FPGA. Other high performance FPGA lowers few to as the only 65 nanometer FPGA, Virtex-5 component core’s dynamic power loss compared to the market in 35-40%. Looks like new on 6-LUT and construction and so on diagonal line symmetrical interconnection innovations, caused the actual core dynamic power loss to further reduce 50% or above. In addition, further reduced the power loss using the quantity unprecedented special-purpose module.
