Abstract: This article introduced briefly realizes the entire digital phase-locked loop (DPLL) principle and the method in FPGA, solves is unstable when the synchronized serial data correspondence’s synchronized clock the quick recovery problem; And introduced with emphasis uses in the digital phase-locked loop which the controllable modulus frequency divider realizes the wideband capture’s method with to realize the process.
Key word: DPLL; FPGA; Digital ring circuit filter; Clock recovery; Wideband
Introduction
The digital phase-locked loop (DPLL) technology in the digital communication, the radioelectronics and so on numerous domains obtained the extremely widespread application. PLL which realizes with the traditional analogous circuit compares, DPLL has the precision high, not the temperature and the voltage influence, the ring circuit band width and the center frequency programming adjustable, easy to construct merits and so on higher order phase-locked loop. Along with integrated circuit technology development, not can only make the frequency high monolithic integration phase-locked loop, moreover may integrate the overall system to a chip comes up. In based on the FPGA communication circuit, may take the entire digit phase-locked loop a functional module to insert in FPGA, constitution internal phase-locked loop. Generally between the synchronized serial port mailing address’s synchronized serial port’s data transmission must have the special synchronized clock line besides the data line, not only this connection mode needs to increase a line, the synchronized performance is been also big the environment influence. May restore the receive position synchronized clock using the digital phase-locked loop from the serial potential flow data. Thus, between the serial port only uses a data line to be possible to receive the synchronized serial data, simplified the serial port connection relations. This article introduced that resumes the serial data position synchronized clock’s design based on the FPGA digit phase-locked loop with to realize and to enhance the digital phase-locked loop performance the measure.
DPLL structure and principle of work
Entire digit phase-locked loop (DPLL) basic structure as shown in Figure 1. Mainly by discriminator DPD, digital ring circuit filter DLF, the pulse addition and subtraction electric circuit (numerical control oscillator DCO) and the frequency divider (controllably changes mold N) four parts of constitutions. The pulse adds and subtracts electric circuit’s clock respectively is 2Nfc, fc is the ring circuit center frequency. DPLL is one kind of phase feedback control system. It acts according to input signal fin and local restores between clock fout the phase error (lag the signal to send in digital ring circuit filter DLF to carry on the smooth filter in advance) to the phase error signal, and produces controls DCO the movement control signal DCS, DCO the instruction which gives according to the control signal, adjusts the internal high speed oscillator’s shake frequency, through the feedback control continuously, causes its output clock fout the phase track data-in fin phase.
Figure 1 entire digital phase-locked loop basic structure
The ring circuit module concrete function and the electric circuit realize
Digital discriminator design
The commonly used discriminator has two kinds, different or gate (XOR) discriminator and border control discriminator (ECPD). Designs differently with general DPLL DPD, position synchronization DPLL DPD needs to remove the potential flow data feeds several position code values maintains the invariable adverse effect continuously. This article uses the advanced version different or gate discriminator, it outputs an expression local to restore the clock in advance or the lag in the input signal phase error. If local restores the clock in advance in the input signal, then/the lag pulse UD output is the high level in advance, otherwise the UD output is the low level, as shown in Figure 2.
Figure 2 advanced version different or gate discriminator schematic diagram and work oscillogram
Obviously, when output signal Fout is in advance, the lag and the synchronization in Fin, the PE pulse’s front is away from Fin the rise along the phase is different.
Digital ring circuit filter’s design
The digital ring circuit filter (DLF) function is eliminates the discriminator output in the phase difference signal PE high-frequency component, guarantees ring circuit’s stable property, as soon as in fact available changes the mold reversible counter (supposes modulus is K) realizes. K changes the mold reversible counter carries on the addition and subtraction operation according to phase difference signal PE. When PE is the high level, the counter carries on adds the operation, if adds together the result achieves the preinstall the mold value, then outputs carry pulse signal DP to give the pulse addition and subtraction electric circuit; When PE is the low level, the counter carries on reduces the operation, if the result is zero, then outputs one to borrow signal impulse DP to give the pulse addition and subtraction electric circuit. When Fout synchronization in Fin or when random disturbance pulse, the counter adds and subtracts number basic equal, the counting result paces back and forth up and down in the starting value place, will not produce carries and borrows the pulse, the phase jitter which because the filtration the stochastic noise will cause. The counter controls the DCO movement according to the output result production the control command.
K changes mold reversible counter mold value K has the very tremendous influence to the DPLL performance index. The counter mold value K value may decide according to the input signal phase jitter, enlarges mold value K, is advantageous in enhances DPLL the anti-chirp ability, but will cause the big pull-in time and the narrow pull-in bandwidth. Reduces mold value K to be possible to reduce the pull-in time, the expansion pull-in bandwidth, but reduced the DPLL anti-chirp ability. In this design chooses K=4. In the initial time, the counter is set at the starting value is K/2=2, like this may the DPLL capture velocity be very quick.
Numerical control oscillator’s design
The numerical control oscillator (DCO) the status which locates in the digit phase-locked loop is equal in simulates in phase-locked loop’s voltage control oscillator. Uses the numerical control oscillator in this digital phase-locked loop design is the invariable pattern frequency divider. Its output is adjustment variable division ratio divider’s mold value N. This value’s size along with each Fin cycle in (when Fin=1) the phase demodulation will output PE to make the adjustment. When UD is the high level, increases invariable frequency division mold value N, adjusts the frequency division output to cause it lagging of phase; When UD output for low level, reduces invariable frequency division mold value N, has adjusted the frequency division output to cause it output phase advance. If the digital ring circuit filter already do not have the steering impulse signal DP output, that frequency division mold value N will maintain invariable, after local restores the signal phase and the input signal phase after the N frequency division’s output is at in-step condition.
Local high speed clock signal CLK the high speed oscillator provides by the piece outside. The clock signal cycle size had decided DPLL in locks under the condition the phase track precision, simultaneously, it also affects DPLL the pull-in time and the pull-in bandwidth. In order to enhance the phase track the precision to reduce data receive the error rate, the clock signal CLK value should be as far as possible high. In this design takes high speed clock signal CLK the oscilation frequency is 64MHz. The numerical control oscillator may realize by a reversible counter.
N frequency divider’s design
The N frequency divider is one simple eliminates the N counter. The N frequency divider adds and subtracts electric circuit’s output pulse to the pulse to carry on the N frequency division again, obtains entire ring circuit’s output signal Fout. At the same time, because of Fout=CLK/2N=fc, therefore may obtain different ring circuit center frequency fc through change frequency division value N. Moreover, the mold value N size has decided the DPLL phase demodulation sensitivity for π/N.
The ring circuit realizes
This design in Altera in Corporation QUARTUSII5.0 development software platform, uses the VHDL language utilization system design method from the top, designs the entire digital phase-locked loop in Altera newest CPLD on chip MAXII240. Finished after the phase-locked loop design, and carried on the simulation, the synthesis, the confirmation through the QUARTUSII5.0 integration environment, DPLL design result like chart 3.
Figure 3 advanced version different or gate discriminator DPLL schematic diagram
And, reversible counter counter2 is ring circuit filter DLF, the preinstall starting value is 12, the addition carrying mold value is 4, the subtraction carrying mold value is 12. Reversible counter lmp_counter2 is the numerical control oscillator, its initialization value is time [3..0], its output namely for phase-locked loop frequency divider’s mold value N, the value of exports size concerns along with the steering impulse signal DP number. In this design, fclk=64MHz, fin=2Mb/s, then time [3..0] =0100b=8. Addition counter lmp_counter2 is the phase-locked loop frequency divider which mold value N is controlled. It is noteworthy that phase-locked loop frequency divider lmp_counter2 carry output Cout cannot take the frequency division output directly, because in the simulation process discovered that along with fclk frequency’s elevation, Cout easy to produce the risk burr, affects the phase-locked loop the stability. Therefore a 4 input rejection gate takes the frequency divider output decision in addition.
In Figure 4 in simulation result, fclk=64MHz, fin=2Mb/s. Simulation input signal Fin is a random binary symbol stream signal. Obviously, regarding many companies 1 or 0 symbol stream signals, this phase-locked loop’s output Fout can restore the clock which accurately continually the synchronization needs. When second input symbol arrival local restored clock Fout already the lock-in synchronism condition, the capture velocity was very quick. Phase lock error most greatly for π/2N=π/16.
Figure 4 advanced version different or gate discriminator DPLL simulation result
Capture band width expansion
Although the above design’s digital phase-locked loop may lock fast, the phase-lock precision is also high, but its catching range is narrow. This digital phase-locked loop biggest phase-shift tunability for ±π, once the input signal Fin phase jitter surpasses this scope or the Fin frequency has the change, the phase-locked loop is unable to complete capture locking automatically. Therefore, must carry on the expansion design to this design, realizes the wideband capture function.
In order to realize the wideband capture, establishes a special electric circuit, determination input signal Fin each bit cycle (or frequency), and determines whether to change, if obtains a bit cycle to change, will control adjusts DCO the output oscilation frequency, will cause it to track Fin fast the frequency, will coordinate the fore-mentioned digital phase-locked loop again the phase track, may complete wide scope frequency locking. Circuitry like chart 5.
Wideband DPLL frequency capture electric circuit schematic diagram
Figure 5 electric circuit and Figure 3 an above electric circuit merge, namely for the complete wideband DPLL electric circuit. Obtains input signal Fin periodic signal time [3..0] to escort to Figure 3 phase-locked loop frequency divider lmp_counter2, controls DCO the output oscilation frequency. This wideband DPLL electric circuit’s capture scope upper frequency fcmax=fclk/4, lowest frequency fcmax=fclk/4M, M is the N frequency divider’s maximum value. In this design, fclk =64MHz, M=16. Therefore the phase-locked loop frequency capture scope theoretical value is 16MHz-1MHz. Corresponds in the input symbol stream speed is 32MHz-2MHz. When Fin=16MHz and Fin=1.6MHz simulation result like chart 6(1)(2).
Figure 6-1 time Fin=16MHz simulation profile
Figure 6-2 time Fin=1.6MHz simulation profile
According to the simulation result, may realize the stable phase-lock’s lowest frequency is 1.2MHz, slightly is higher than theoretical value 1MHz; The achievable highest phase-lock frequency is 16MHz. Capture time 1 Fin cycle.
Conclusion
In the general digital phase-locked loop design, “the capture time” and “the capture band width” these two essential performance index is mutually contradictory, any target’s enhancement can sacrifice another target is a price. This article introduced the wideband scope digit phase-locked loop used simply completes slightly realizes the capture time to catch the band width the quite wide entire digital phase-locked loop, has solved “the capture time” and “the capture band width” the target mutually contradictory question. And “the capture band width” the target may further expands through in the enhancement work clock fclk frequency as well as the phase-locked loop counter counter capacity. Because this digital phase-locked loop may use in directly the synchronized serial communication the binary symbol stream synchronized clock’s restoration, but the automatic tracking receive symbol stream speed’s transformation, simultaneously this design is based on the FPGA modular design, is advantageous for other number system design the transplant and the integration, is specially in has the vital significance in other digit application system based on the FPGA communication circuit.
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