Abstract: This article introduced one kind practical based on the FPGA ethernet video frequency broadcast receiving system, because has used the FPGA technology, causes the system structure to be simple, the reliability is high. Finally has carried on the profile simulation, finally has indicated the design accuracy.
And: The lead code uses in the physical signal the synchronization, is 7 byte 10101010 sequences and 1 byte 10101011 sequences; What destination address and source address use is the MAC address, the first 3 bytes are called Block ID, it symbolized that production equipment’s factory and evaluates by IEEE; The latter 3 bytes are called equipment ID, it evaluates by the factory, moreover always only; Data length purport transmission data total length; The data and the stuffing character may from 0 to 1 500 bytes different, if the actual data is smaller than the smallest length which needs, MAC will supplement some invariable stuffing character (PAD), maintains 64 byte smallest frame scales. If the data is longer than 1 500 bytes, then high-level (will be generally third) will divide into the data field the different frame to carry on the transmission; The frame verification uses for to guarantee that carries on the correct transmission, the cyclical redundancy check (CRC) uses for to carry on the effective frame the inspection. In the ethernet data packet’s data part, contained has planted the level agreement respectively first. In this article system, has contained IP first and UDP first.
3. medium irrelevant connection (MII)
MII is one uses in interlocking the controller and the transceiver brand-new medium irrelevant connection, it is a 100 Mbit/s fast ethernet development work constituent. This connection has provided the new physical connection mechanism as well as the controller and the transceiver function division. This connection mainly of below some signal make-up:
(1) sending signal
Including half byte width (Nibble-wide) the transmission data signal, is in addition related transmission clock, transmission permission signal and transmission error signal. The data with the clock synchronization, the clock rate is the data rate 1/4 (i.e. 100 Mbit/s ethernet with 25 MHz clocks), the sending signal uses in the data moving from the controller to the transceiver, then the code delivers on concurrently LAN.
(2) received signal
In addition including half byte wide receive data, the receive clock which, the receive data desired signal and the receive error signal is related. The data uses the clock synchronization, the clock rate is the data rate 1/4. The received signal uses in the data which will decode from the transceiver moving to the controller.
(3) ethernet control signal
These signals are by the transceiver production carrier interception and the collision detection signal, uses in the controller making the medium access control. They only use in the half-duplex pattern, is neglected in full-duplex mold in the formula.
(4) management signal
Serial manages the I/O signal and the related clock signal including one. Uses in management information which the two-way alternate disposes between the controller and the transceiver and controls.
Third, system design
This system realizes overall diagram as shown in Figure 2.
And what the ethernet connection uses is the traditional RJ45 connection, the 10M/100M transceiver may use DM9101 monolithic to realize, what the FPGA part uses was Xilinx Corporation’s Spartan II series chip, the MPEG-1 decoding chip has used the C-Cube Corporation’s decoding chip. uses the MII standard the 10M/100M transceiver to FPGA between the connection, uses the I2S form FPGA to the MPEG-1 decoding chip between the connection.
1.DM9101
DM9101 is a physical level, monolithic, low power loss 100Base-TX and the 10Base-T operation switch. One side medium this, it already to use in 100Base - the TX fast ethernet’s non-shielded twisted pair providing a direct connection to (5 kind of coaxial cables), also to use in 10Base-T ethernet’s UTP5/UTP3 providing the direct connection. Through the IEEE802.3u medium irrelevant connection (MII), DM9101 might (MAC) the level connect with the medium access control, has guaranteed between the different producer’s product high interoperability.
This chip integrated the MII standard interface, the 100Base-TX transmission/receiver, the 10Base-T transmission/receiver, the automatic consultation, the collision detection, the carrier interception, 4B5B to arrange/the decoder, Canada/Xie Raoqi, the serial port and between mouth functions and so on transformation.
Because has used the MII standard interface, causes the designer to be possible to carry on the establishment through this connection management holding wire to this chip register, thus completes to 10 Mbps and 100 Mbps two speed choices, has highlighted the design flexibility.
2.FPGA design
Because must enable the data in the ether on-line transmission, the server end’s calling order should the data which must transmit carry on the pack (or seal). In this system must transmit data for video data (VCD data), but the VCD data is generally deposits by the dat form in the compact disc. Therefore deals with the data packet which in the receiving end receives to carry on the bale breaking, simultaneously and completes the function which the data format transforms, causes to deliver the MPEG-1 decoding chip the data format is the dat form data, thus carries on the decoding, finally uses the ordinary television to be able to receive.
Therefore this part mainly must realize the function is: Completes the ethernet data frame which docking receives to carry on the bale breaking first, takes out the seal in the ethernet data frame data part, then divides another interpretation IP data packet and the UDP data packet again, true has the VCD broadcast form data to take, passes through one advanced to leave (FIFO) the buffer to output the MPEG-1 decoding chip first to carry on the decoding. And in the bale breaking process, must carry on the verification to the data, verifies the correct data packet only then to carry on the transmission, has used the direct discarding method regarding the verification not correct data packet, uses the verification algorithm is the cyclical redundancy check algorithm (CRC).
Design diagram as shown in Figure 3.
(1) the leader examines: When the system examined presented 15 nibble continuously 1010, when simultaneously afterward nibble was 1011, explained that an ethernet data frame started, should make further processing to this part of data.
(2) group byte: Because comes out from the DM9101 chip the data signal is by four bytes (nibble) form transmission, thus must carry on the group byte manipulation to it, every 2 nibble composes a byte, what the concrete operations process rests on is in the MII frame structure byte composition form carries on.
(3) CRC verification: To the ethernet frame’s destination address, the source address, the length, the data carry on the CRC verification, and carries on the comparison with the frame final four bytes, if is consistent, namely for correct ethernet data; If is inconsistent, then discards this.
(4) MPEG-1 data: Takes out in the ethernet frame the length byte value, initializes a counter with this value, thus enters to the data
The line of counting control, takes out MPEG-1 form the valid data.
(5) FIFO: Because the ordinary ethernet’s data transfer rate is 10
Mbps or 100 Mbps, but carries on time the MPEG-1 decoding the speed is about generally 1.5 Mbps, thus must make the speed setting to the data stream. This FIFO used the Spartan II series chip internal storage module to carry on the buffer directly.
(6) with pier examination: the dat form’s data frame has one with the pier is: 00FFFFFFFFFFFFFFFFFFFF00 (hexadecimal system), when examines should with the pier, indicated that a dat data frame started, should after that the data together with should output together with the pier information to the decoding chip.
(7) serial output: Finally data conversion which obtains for serial data, and outputs by the I2S form the data and the clock equisignal in the MPEG-1 decoding chip to carry on the decoding.
Fourth, simulation result
1. group of byte simulation result
The data composes a byte from 2 nibble simulation result as shown in Figure 4. And, the CLK signal is 25 MHz clock signals, DA is the data signal which is composed of 4 bit data, they output by the DM9101 chip; After DATA is composes the byte 8 bit data signal, CLK-B is the Byte clock signal which obtains by the CLK signal two frequency divisions.
2.I2S form simulation result
By I2S form output’s data’s simulation result as shown in Figure 5. In the simulation uses the form is: 32 BCK, MSB first, the right channel is the low level. And BCK is the position clock signal, LRCK is about the clock choice clock, DATA is VCD form MPEG-1 regards/the voice data.
Fifth, subtotal
This system uses the FPGA chip is Xilinx Corporation’s Spartan II series chip, develops with the Foundation software tool. After the design input completes, carries on the whole the translation and the logic simulation, then carries on the transformation, the layout, the time delay simulation production configuration files, finally downloads to the FPGA component, realizes its hardware function. Because system’s many functions realize together by FPGA, the periphery component are very few, therefore the system volume is small, the reliability is high, and component’s programmable causes the system function easy to consummate. The simulation result indicated that various signals’ logical function and the succession coordination has achieved the design requirements completely.
Reference
[1] IEEEStandard 802.3. (2000 Edition) [S].
[2] the leader work room translates the .TCP/IP technology comprehensive work [M]. Mechanical industry publishing house, 2001.
[3] the court attendant wave, Huang Dongquan, and so on translates 0. ethernet technologies and the application [M]. Mechanical industry publishing house, 2000.
[4] Liu Yumin. Compact disk (CD, VCD, DVD, LD) technology base course [M]. Electronics industry publishing house, 1998.
