1 introduction
The I2C main line is between the chip which Philips Corporation promotes the serial transmission main line. It only used the serial data line (SDA) and the serial clock line (SCL) two segments has then realized the perfect full-duplex synchro data transmission, and might constitute the multi-computer system and the periphery component very conveniently expands the system.
This article introduced that uses in the I2C bus system in the P87LPC764 monolithic integrated circuit typical LCD actuation control component PCF8577C to expand 256 section of static LCD the circuit design method.
2 hardware circuit design
2.1 P87LPC764 monolithic integrated circuit’s I2C bus interface
P87LPC764 is one kind of small seal which, the low cost, the high performance monolithic integrated circuit Philips Corporation produces (actual content sees reference 2). It uses the 80C51 acceleration processor structure, internal has supports the I2C main line’s hardware interface. When activates the I2C main line, P87LPC764 port 1 P1.2 and P1.3 may serve as SCL and the SDA main line function separately. Its I2C main line controls by 3 special function registers, namely I2C control register I2CON, I2C disposition register I2CFG, I2C data register I2DAT. Various registers form and the position meaning are as follows.
a.I2CON register
The I2CON register everybody’s meaning when carries on the read-write operation is completely different. Below introduced separately it reads, writes the operation form.
Each function is as follows:
RDAT: Data receive position. When SCL line rise along on-line gains by SDA. Reads when the RDAT position does not eliminate DRDY, also does not release the SCL line.
ATN: When in DRDY, ARL, STR or STP random one is 1, ATN sets 1. Through tests the ATN position to be possible to judge on the main line whether to have some kind of event.
DRDY: Data preparation the flag bit. In the SCL rise along the time setting, the read-write I2DAT register or reads in 1:00 to CDR clear 0. ARL: Bus arbitration defeat flag bit.
STR: Starts the flag bit. When examines the start condition sets 1.
STP: Stops the flag bit. When examines the stop condition sets 1. MASTER: When this component becomes the I2C main line master controller sets 1.
And:
CXA: Reads in 1, clear data transmission mode.
IDLE: Reads in 1, is controlled must examine when the next start position only then receives the bus message.
CDR: Reads in 1, eliminates DRDY.
CARL: Reads in 1, eliminates ARL.
CSTR: Reads in 1, eliminates STR.
CSTP: Reads in 1, eliminates STP.
XSTR: When installs primarily the controller, reads to XSTR and CDR 1, causes the I2C main line transmission redundant start position.
XSTP: When installs primarily the controller, reads to XSTP and CDR 1, causes the I2C main line transmission stop position.
b.I2CFG register
SLA: Reads in 1, this installs into the I2C main line to be accused.
MASTRQ: Reads in 1, this installs into the I2C main line master controller.
CTI: Reads in 1, eliminates the timer 1 overflow symbol.
TIRUN: Reads in 1, the timer 1 starts to move; Reads in 0, stops the timer 1 movement and the timer clear 0.
CT1 and CT0 use for to decide the SCL on-line height level the smallest time.
c.I2DAT register
The I2DAT register reads, writes the form is different.
And RDAT is the data receive position. When SCL line rise along gains from SDA. While reads the data from I2DAT RDAT, may eliminate DRDY and the establishment transmission state of activation.
And XDAT is the data transmission position. Next must transmit the data reads in this position. When writes XDAT, should eliminate DRDY and the establishment transmission state of activation.
2.2 I2C main line display device PCF8577C
a. pin function
PCF8577C is in the I2C bus system the typical LCD actuation control component, when effusive type may actuate 32 section of LCD; When two-stage way may actuate 64 section of LCD. If uses many piece of cascades, then may constitute 256 section of LCD display system most greatly. Moreover, PCF8577C also has the demonstration data auto incrementing to read in the function, moreover programs very simply. PCF8577 pin arrangement as shown in Figure 1. Various pins function is as follows:
S32~S1: Section output port.
BP1: The back outputs extremely. When cascade may take the synchronized input end, meets the first level of BP1 signal to take the synchronized signal.
A2/BP2: Under the static state drive type, this end takes hardware address wire A2, uses in establishing 8577C the hard item address. Under the two-stage drive type, this foot serves as the second back to output BP2 extremely. When cascade as the synchronized input end, meets the first level of BP2 signal to take the synchronized signal. Under the double-pole way, its hard item address only decided by A1 and A0.
A1: Hardware address wire. Internal does not have pulls the electric circuit, cannot be hanging.
A0/OSC: This foot needs the external connection resistance electric capacity to constitute the oscillator, this time A0 was stipulated that for logic 0, serves as the hardware address wire. When cascade, except the first level outside, the oscillator which other all levels of external connection resistance electric capacity does not constitute, but receives VDD or the VSS establishment item address.
VDD and VSS: Respectively is the power source, the cathode.
SCL and SDA: Respectively is the I2C main line’s clock and the data line.
b. data manipulation form
8577C has nine registers, its operation form as shown in Figure 2. Below controls the register and the section byte register explained.
* controls the register
Controls the register to use in the microprocessor entering the second byte to a 8577C data transfer process Chinese dress (control byte). Control word each meaning is as follows:
MODE: Drive type choice position, “0″ for choice static state drive type; “1″ for choice double pole drive type.
BANK: The data access position, “0″ for the choice demonstrated that a body data, “1″ demonstrates the B body data for the choice.
V5V4V3: These three correspond with the hard item address. If component from address and on I2C main line from address match case, and V5V4V3=A2A1A0, then this component is selected, this time then receives the data which on the main line sends, and loads it the section byte register, otherwise does not give pays attention. Under double pole drive type, because A2 makes BP2, therefore V5 is invalid.
V2V1V0: The section byte register SBR address position, uses for to decide that which SBR reads in the section data.
May compose section byte vector SBV with V5~V0, it has the auto incrementing function. If needs one time to transmit many section byte data, but after is loading a section byte data every time then the SBV automatic Canada 2 (effusive type) or adds 1 (two-stage way), with the aim of loading the next data; When cascade, when after piece of 8577C packs, the SBV auto incrementing, and aims at the hard item address with it neighboring next 8577C SBR. The SBV value may circulate the trundle between 111111~000000.
* section byte register SBR
Eight SBR separable becomes two groups, the address is called a body for an even number group, the wonderful array is called the B body. Under the effusive type, either demonstrated that a body data, either demonstrates the B body data. May through change the BANK position the value to cut the demonstration content. Under the double-pole way, eight SBR will use also, by now BANK was does not care about the code, a body corresponds to the BP1, B body corresponds to BP2.
c. main line operation
PCF8577C main line operation including from address and hard item address, from the address fixed is 0111010, altogether seven, are the I2C main line committee assigns. In addition, but also three hard item address (A2A1A0) treats the hypothesis. If in the application system has many piece of 8577C, then must establish the different hard item address to come separately to distinguish. Those who select 8577C to refer to is it is selected from the address and the hard item address.
And: After the start signal S first byte’s most low position is the direction position, because 8577C can only receive the data, therefore this must be 0; Other seven are from the address. If system including many piece of 8577C, then each piece can makes the reply to first and the second byte; But after the section data byte’s answering signal by is only selected chip production. The data byte may continuously many. If only changes the BANK value, but does not change in SBR the content, should after the control byte reply position transmits stop signal P, by now the chip which will select will be renewed BANK.
2.3 display circuit design
Expands LCD using P87LPC764 interface circuit as shown in Figure 3. This electric circuit uses the static state drive type, visits 8 piece of 8577C by the P87LPC764 monolithic integrated circuit to be composed the biggest cascade system. Each piece of 8577C may actuate 32 section of LCD, therefore, altogether may expand 256 section of LCD. But when cascade application, only by the first level of constitution oscillator, outputs the back extremely signal, and carries on the synchronization after the level.
3 software designs
Ought to use electricity the road is a list advocates the I2C bus system, the data transfer operation only then the main transmit mode, thus has not examined the main line in the programming process to be wrong. When data transmission, transmits 1 byte every time, should examine the answering signal, if the non-answering signal, establishes flag bit F0 to reissue the data. This electric circuit uses the effusive type, the demonstration is a body data.
If in procedure uses for demonstration buffer 30H to the 7FH unit to deposit the glyph code, then this I2C main line display circuit’s procedure detailed list is as follows:
4 concluding remark
This article introduced in the I2C bus system expands the LCD monitor’s electric circuit and the programming using model LCD actuation control component PCF8577C. Reference this article mentality, may also realize the dynamic LCD monitor’s expansion. This method carries on when the I2C bus system the man-machine interface circuit designs has the good reference value.
