MIL-STD-1553B is one kind of time division system, the order/response, the common control type multiplex half-duplex serial data trunk, its transmission speed is 1Mb/s, the word length is 20b, the data effective length is 16b, the information content greatest length is 32 characters. Its information format has bus control unit BC (Bus Controller) to remote terminal RT (Remote Terminal), arrives at RT RT to RC, RT, the broadcast type and the systems control type.
The MIL-STD-1553B main line agreement already developed into the internationally recognized data bus standard, widely applies in the avionics system ensemble, at present domestic and foreign development each kind of 1553B main line gathering card, what mostly uses is American DDC Corporation produces the BU-6150 connection chip, but this chip price is quite expensive, the development cost is high, another many businesses look are popular sigh. This article introduces based on the DSP 1553B main line communication module design, uses TI Corporation TMS320F206DSP chip to carry on the digital signal processing, carried on the scene with FPGA to program repeatedly, reduced the designed cost, has met the 1553B communication module development need.
1 TMS320F206 synopsis
This 1553B main line communication module’s DSP uses TI Corporation’s TMS320F206, uses for to realize the 1553B main line agreement main body part, realizes character and news functions and so on processing, TMS320F206 is one kind of performance-to-price ratio high fixed point DSP chip which TI Corporation promoted in recent years, used the static CMOS integrated circuit craft manufacture to become, the DSP chip advanced Harvard structure permission program memory and the data-carrier storage independent address, the independent visit, two main lines might permit the data and the instruction read also carry on, thus made the data the turnover rate to enhance one time; The special-purpose set of instructions has provided the function formidable signal processing operation. The TMS320F206 main feature is as follows:
when (1) 5V working voltage, 20MHz basic frequency, instruction cycle 50ns; 3 exterior pin interrupts; 8 level of internal hardware storehouse, depositing transfers/the interrupt return address; Hardware waiting; Dormancy IDLE pattern, low power loss; Standard IEEE1149.1 artificial mouth.
(2) the internal 64k procedure space, the 64k data space, the 64kI/O space, the 32k overall situation storage space, internal 544×16b double addressing RAM,32k×16b user programmable FLASH, takes the procedure space, 4k×16b single addressing RAM, before procedure space and data space, may carry on the data removal.
(3) the internal 16b timer, on the piece waits for the producer softly, may respectively be the procedure space, the data space, the I/O space has 0-7 waitings, on the piece the oscillator and the phase-locked loop has the frequency multiplication and the frequency division function, the 32b arithmetic logic unit/accumulator, 16×16b the multiplier, full-duplex asynchronous serial port UART, the enhancement synchronized serial port, brings 4 level of FIFO.
2 system’s composition diagrams and principle of work
The instrumentation uses the monolithic integrated circuit technology, the programmable logical component (FPGA) the technology, the digital signal processing (DSP) the technology, unifies the 1553B main line receiving and dispatching technology development to become. May also carry on the off-line examination to the single aviation electronics, may also and records equipment’s data transmission to airplane’s entire main line’s movement to carry on the online examination one by one. The instrumentation whole uses the personal digital assistant (PDA) the technology, the data feeds, the output, processing, the control, the demonstration and so on concentrates in the instrumentation.
System composition diagram as shown in Figure 1.
From data signal flow aspect: When receives the data, after the exterior data delivers the transceiver carries on the voltage transformation, becomes group of 20b the serial data, processes the 16b parallel data after FPGA chip EP20K200 to deliver the DSP processing after the expansion mouth, then carries on the data buffer after pair of mouth RAM, when needs to demonstrate the data, monolithic integrated circuit CPU the 16b parallel data which sends to pair of mouth RAM carries on the analysis to save, transforms the hexadecimal system according to the request, the binary system or the engineering system of units delivers the monitor to demonstrate, when sends the data, CPU keyboard entry’s data according to the hexadecimal system, the binary system or the engineering system of units after the transformation evacuation pair of mouth RAM buffer, DSP from the pair of mouth RAM read-in data, pretreatment evacuation EP20K200, EP20K200 carries on again transformation processing, outputs group of 20b the serial data to arrive at the transceiver, becomes after the live pressure coupling conforms to the 1553B standard request serial data, passes through the receiving and dispatching connection to transmit again to the data bus on.
3 hardware circuit design
3.1 receivers and transmitter
in 1553B avionics system, what between various terminal device and the main line uses is the coupling way, divides into the transformer coupling and the conductive coupling, uses American DDC Corporation’s BU-63152 chip, has two completely independent double redundancy ports, satisfies the request which completely the 1553B main line receives, sends, under the receiver operator schema, under the pin STROMB control, the data is turned the bidirectional TTL level, outputs from RX DATA OUT and his/her non-foot to under first-level decoding circuit, under the transmitter operator schema, under the pin INHIBIT control, the transmitter part from the encode circuit receive data, transmits to the data bus on.
3.2 FPGA modules
Unifies the FPGA technology and the digital signal processing DSP technology is in the modern electron design the commonly used method, in this module’s FPGA chip connection mainly realizes the following function:
(1) the processor may process changes into main line’s on serial information circulation the parallel information which or with it is opposite;
when (2) receives or the transmitter data, can distinguish or the production standard 1553B information word and the news.
(3) completes with processor’s between exchange of information, including 1553B information address assignment, order character (either condition character) decoding or returns condition character, transmission data character and so on.
Realizes the codec encoder-decoder with FPGA, its basic function the BU-61580 chip which mentioned with front is similar, is this 1553B main line instrumentation’s key technologies.
3.3 DSP modules
TMS320F206 is a section of designed cost which TI Corporation recent years promoted is lowest, structure function order of complexity also low fixed point DSP, internal 32k FLASH,4.5k RAM might satisfy the processing scale moderate duty, in this instrumentation the DSP module’s design was mainly to the clock circuit, the interrupt as well as the data and address bus’s connection technology assurance, its main interface circuit as shown in Figure 2.
May see by the DSP connection circuit diagram, the DSP module has provided the clock circuit for the overall system, the DSP chip interrupt by the EP20K200 production, on the one hand informs the F206 read data, on the one hand informs DSP to carry on the error processing, as a result of the DSP chip’s stream line operation way, the digital signal processing speed function was formidable, has satisfied the 1553B agreement transmission speed major characteristic.
3.4 pair of mouth RAM and display module
Because easy to create the data jamming phenomenon in high speed data processing and the gathering system, the high speed data connection’s design is playing the vital role unimpeded to the overall system data transmission, in this design uses American DDC Corporation’s 8k pair of mouth static state RAM IDT7025 has solved the data jamming problem.
The display module used one kind of memory in this design to meet the display module the hardware connection mode. DSP will want the data which demonstrated to send in the pair of mouth RAM,51 monolithic integrated circuit to scan the memory unceasingly, makes corresponding processing according to the memory in data, on the unceasing refurbishing display monitor’s content, the double mouth RAM BUSY holding wire to avoid controlling at the same time the port to write the operation to the identical memory cell to provide the hardware support. In the design the liquid crystal display module uses 16×16 the lattice Chinese display module.
4 system software designs
This 1553B avionics main line instrumentation software design mainly includes 3 major parts, with actuates the data acquisition board card, completes to various registers’ disposition, realizes the data receiving and dispatching examination.
4.1 FPGA control procedure
This part uses hardware description language VHDL to carry on the programming, carries on the synthesis with Synplify, as well as uses Max Plus II to carry on the succession simulation, realizes in the MIL-STD-1553B bus interface Manchester code code, the decoder on FPGA, this logic may realize by the state machine, may divide is 4 conditions carries on; The 1st condition line is the idling condition, when examines the data jump along, enters the 2nd condition; The 2nd condition for effective synchronized prefix examination condition; When examines the effective synchronized prefix, starts the 3rd condition, with the phase-locked loop separation clock, carries on the code pattern transformation; When the data is effective enters the 4th condition, carries on and/the string transformation and the parity check. FPGA receive data flow as shown in Figure 3.
4.2 DSP modular control procedure
The DSP part’s software uses the C language and the assembly language mix programming, namely has the C language probability strong characteristic, also has the assembly language to carry out the speed quick and the direct-viewing characteristic, in this design the DSP software design mainly completes to FPGA and its intercom register initialization; To the FPGA transmission data’s time control command operation, accepts when the data orders the character, condition character processing, as well as informs FPGA to accept the data and so on, is the overall system control hard core. Figure 4 gives the DSP software control flow chart.
5 conclusions
Mainly uses in the army aviation electronics based on the 1553B main line’s avionics instrumentation online and the off-line examination, simultaneously satisfied BC and the RT function, the PDA design to examines has also provided the enormous convenience, because certainly designed is at the prototypical stage, but also had some imperfect place, present’s improvement space will be quite also big.
