In the modern automobile electron, has many micro controllers to be together coordinated generally works. The DSP controller uses the Harvard structure, the operating speed is quick, therefore widely uses the DSP chip in the automobile electron to realize the automobile dynamic system’s control. ARM is one kind of 32 micro controllers, has rich outside to expand the connection, therefore realizes the big Rong Zui data storage and the man-machine interaction or the GPS global positioning system generally in the automobile electron with ARM, therefore needs to carry on the data exchange between DSP and ARM.
CPLD (Complex Programmable Logic Device) is one kind of complex user programmable logic component, because uses the hardware programmable technology, thus causes not to count the hardware circuit also likely to design the software to be equally convenient. DSP2407A is T1 corporate design one section to satisfy the wide range specially the digit motor control application micro controller. S3C4480 is Tristar Corporation to grasp the equipment design the high performance-to-price ratio micro to press out the regulator specially. This design take Xilinx Corporation’s XC95108 as an example, through opens 2 independent SRAM regions in CPLD (each 1 byte) to realize DSP2407A and the S3C4480 parallel correspondence. Uses this mailing address, the data transmission is accurate, is high speed, basic may satisfy DSP2407A and the S3C4480 bus interface real-time communication request, thus organically unifies the complete bikes power control and the man-machine interaction.
1 integrated system structural design
DSP2407A is responsible to gather automobile all data, issues S3C44B0 the data through CPLD to carry on again the data storage and the man-machine interaction. Sometimes S3C4480 must receive the touchscreen order, the order also issues the DSP2407A controller through CPLD, thus controls puts in order the Taiwan automobile’s movement. To DSP2407A, must respond the order which promptly sends by S3C44B0; But regarding S3C4480, must momentarily receive the data which DSP2407A sends, like this, intercommunication’s timeliness must be very strong. Therefore in the system design, DSP2407A with the interrupt mode receive data, S3C44BO uses the inquiry way receive data.
In DSP2407A, [DO~D7] is the data line, [A15~A12] is the address wire, Is the I/0 space selection pin, when visits the exterior memory or the I/O space is the low level. We are writes enables, RD is reads enables. IOPC7 the foot general I/O pin, uses for to judge DSP2407A whether can write the data toward CPLD. When IOPC7 is the low level, represents DSP2407A to be possible to write the data toward CPLD in; If is the high level, then expressed that in CPLD had the data, by now DSP2407A could not write the data toward CPLD. XINT1 is the external interrupt, uses for to inform DSP2407A to prepare to read in CPLD the data.
In CPLD, realizes with l piece of XC95l08. XC95108 altogether has 108 great units, has the enough space to realize 2 8 SRAM areas; Mainly uses for to realize between DSP2407A and the S3C44B0 data exchange, has not set at DSP2407A and S3C44B0 reads/writes the control the status byte. In S3C44B0 ‘ [D0~D7] is the data line, nGCSl is the chip select signal, when memory address when corresponding section address region the chip is activated. nWE is writes the permission signal, nOE reads the permission signal. IOPF0 is the general I/O mouth, uses for to monitor whether to read the data from CPLD: When it for high level, represents in CPLD to have the data, may read the data; When it is the low level. Expressed that in CPLD does not have the data to be possible to read. IOPF1 is the general I/O mouth, uses for to monitor whether to write the data to CPLD in: When it for high level, represents in CPLD not to have the data, may write the data to CPLD in; When it for low level, represents in CPLD to have the data, S3C44B0 cannot write the data to CPLD. System structure as shown in Figure 1.
2 CPLD designs
Uses Xilinx ISE8.1 is designs the tool, compiles the source program with internationally the general VHDL language.
2.1 8 bit data transmit from DSP to ARM in
When [A15~A12] is 1100, DSP2407A starts to CPLD to write the data, juxtaposes dspsign_write and armsign_read is 1; Expressed that in CPLD already had the data, informs S3C4480 to be possible to read the data and DSP2407A cannot write the data temporarily to CPLD in; Meanwhile reads in the data in latch sraml.
When ARM sends out the read data signal, starts to read out the data from sraml, and sets at dspsign_write and armsign_read is time 0, indicated that in CPLD did not have the data, DSP2407A might write the data to CPLD.
2.2 8 bit data transmit from 83CA480 to DSP2407A in
When S3C4480 writes the data to CPLD, reads in latch sram2 the data, simultaneously sets at dsp_int is 0, informs DSP2407A to have an external interrupt, may take the data from CPLD; Sets at armsign_write is 0, indicated that in CPLD had the data, S3C4480 cannot write the data again to CPLD.
When [A15~12] is 1101, DSP2407A sends out a read signal to CPLD, the data transmits from latch sram2 for DSP2407A, and sets at dsp_int is 1, armsign_write is l, indicated that the data was read by DSP2407A, S3C4480 may continue to CPLD to write the data.
3 S3C4480 and DSP2407A correspondence software design
In this procedure, DSP2407A uses the interrupt mode receive data, S3C4480 uses the inquiry port way receive data.
(1)DSP2407A procedure
(2) S3C44B0 procedure
