Along with the large scale integrated circuit and the high speed figure signal processor’s development, the correspondence domain’s signal processing more and more puts in the digital territory to realize. The software phase lock technique is a research subject which the development and the high speed DSP appearance develops along with the software radio. The phase lock technique which uses in the software radio receiver is and so in the general programmable component realizes the form based on the digital signal processing technology in DSP, because this type phase-locked loop’s function mainly realizes through the software programming, therefore may be called it the software phase-locked loop (software PLL) [1].
Although the software phase-locked loop uses the primary algorithm thought and the simulation phase-locked loop and the digital phase-locked loop compare not the too sweeping change, however it realizes the way completely to be actually different. This article will establish the software phase-locked loop the Z territory model, analyzes in the software phase-locked loop under the time delay estimate, the capture speed and the multi-speed condition software phase-locked loop model question [1].
1 software phase-locked loop fundamental model
In simulation phase-locked loop foundation, use digit, between analogous system each other’s relation, take second-order two phase-locked loops as example establishment software phase-locked loop Z territory model. The literature [2] have given the phase-locked loop fundamental model and the principle in detail.
If uses the phase-locked loop basic part the software programming the form to realize, may obtain the software phase-locked loop basic composition, as shown in Figure 1.
First embarks from the simulation phase-locked loop’s S territory model obtains the software phase-locked loop Z territory model (the second-order two simulation phase-locked loop S territory model please to refer to the literature [2]). Because the bilinear transform is relates the analogous system and a number system’s important method, has the transformation to be simple, and expression clear perspicuity characteristic [3], therefore this article chooses the bilinearity method of transformation to take between the simulation phase-locked loop and the software phase-locked loop transformation foundation.
Type (1) is the bilinearity method of transformation duplicate frequency range expression:
And: T is relates the number system and analogous system’s sampling time gap, 1/T expresses the sampling frequency. According to this transformation relations, carries on the transformation to the S territory model various part of correspondence’s digital duplicate frequency range expression, may obtain the duplicate frequency range model which as shown in Figure 2.
In the practical application, the second-order linear system often uses the damping factor Xi, the non-damped oscillation frequency ωn description. In the second-order two phase-locked loops, τ1, τ2, K and Xi, ωn between corresponding relationships are as follows:
And type in (2) foundation carries on the equivalent transformation in type (1) to Figure 2, may obtain the software phase-locked loop another linear phase Z territory model, as shown in Figure 3.
In modelⅠ, The parameter τ1, τ2 and K with realizes the electric circuit function resistance, the electric capacity, the pressure to control the oscillator to be closely related. But realizes the software phase-lock function is actually the multiplier, the accumulator and the register, therefore uses the modelⅡThe attribute software phase-locked loop linear phase Z territory model appears has the practical significance.
2 software phase-locked loop mathematical model
The digital discriminator’s Z territory model is as follows:
Realizes one of digital discriminator methods is draws support from the signal the orthogonal decomposition, Figure 4 is this method functional block diagram.
And: LPF expresses the low-pass filtering, A is the constant gain which the low pass filter brings. Therefore discriminator output:
Obtains the digital ring circuit filter’s time domain expression after the counter-Z transformation is:
Obtains the numerical control oscillator’s time domain expression through the counter-Z transformation:
The variable uc(nT) value is small, and the change cannot be too quick, therefore type (14) establishment:
Comprehensive (11), type (12) and type (13), obtains the NCO output signal expression:
If by digital frequency description numerical control oscillator, then calls its digit center frequency ω0T, digital bias frequency for ωn2 · uc(nT) · T. Therefore, this numerical control oscillator’s sensitivity and the digital sensitivity respectively are
· T.
under more than 3 speed condition software phase-locked loop
In the digitized receiver, bumps into under the multi-speed condition frequently the sampling rate transformation question. The so-called multi-speed system is refers to a number system has 2 or 2 above sampling rates [4]. Constitution software phase-locked loop discriminator mixer usual work in systematic sampling frequency. In satisfies the Naikuisite sampling law under the premise, the digitized receiver’s system sampling rate reaches as high as several 10 M generally. But digital discriminator constituent counter-tangent table, because after the mixing data undergoes the multiple extractions, the operating frequency already dropped to and the signal baudrate close level. The data extract simultaneously also reduces DSP the operand, completes the ring circuit filter’s processing speed approximately equal signal baudrate by DSP. In addition because in the software phase-locked loop’s numerical control oscillator needs to provide the similar speed to the mixer the orthogonal carrier, its working speed and the mixer are equal, needs to carry on interpolates the trimming speed.
To use the DSP limited computing resource reasonably, always in satisfies under the premise which the synchronization needs to cut the ring circuit filter’s working speed as far as possible, is also the usually called ring circuit frequency. The ring circuit frequency is a software phase-locked loop key parameter, he simultaneously is deciding the phase-locked loop algorithm computation load and the capture speed. The ring circuit frequency will be excessively high will bring the extra computation burden, the ring circuit frequency is too low cannot satisfy the capture speed the need, will usually take the system baudrate in the application to take the ring circuit frequency the size. This extended model correspondence’s linear phase Z territory model as shown in Figure 5.
And: D expresses the data extract, I expression data interpolation. Data before extraction must carry on the anti-aliasing filter first, may use in the anti-aliasing filter’s FIR filter having the CIC filter, half belt filter and so on.
In actual situation, because the zeroth order maintains the interpolation does not need the extra operand nearly, therefore is used frequently. In fact ring circuit frequency fL can always follow the ring circuit filter output signal the change speed. In other words, carried on the sampling to the ring circuit filter output signal according to the fL speed to retain his complete information, therefore the zeroth order will maintain the interpolation will not have the too tremendous influence to the system performance [4].
Unifies the above software phase-locked loop the basic principle, below with the aid of the Matlab simulation observation software phase-locked loop system response. This article takes the input by the frequency step signal, observes the software phase-locked loop the system response, thus further confirms a series of software phase-locked loop model which this article establishes.
Establishes the systematic sampling frequency is 1 MHz, simulation time 0.1 s, signal center frequency 125 kHz, the outset phase - π/4, input frequency step 100 Hz, the initial station is 0.02 s, the extraction factor is 8. In the ordinary circumstances, hoped that the ring circuit work in the Underdamping condition, takes the damping factor ξ=0.707, ωn by 2πΔF (catches band width to decide quickly) [2], take separately 2π*40,2π*50,2π*100. The simulation leaves the phase error response curve, the NCO bias frequency curve and the frequency step signal phase curve, as shown in Figure 6.
May see from Figure 6, the software phase-locked loop in [0,0.02] the sector the phase error is 0, is at the fixed condition. In t=0.02 the s time, the input signal frequency has had the size is 100 Hz steps, causes the software phase-locked loop to enter the capture process. As a result of software phase-locked loop correcting action, when ωn=2π*50, the system in t=0.05 the s time heavy also the lock-in synchronism condition, the phase error as before is 0. By the phase error response curve may see that the phase-locked loop may the non-difference tracking frequencies step signal, simultaneously indicate that although the phase-locked loop phase demodulation error is 0, but because the ring circuit filter’s true integration affects its output the control signal is not 0, had 100 Hz bias frequency by this control signal to guarantee the NCO output and the input signal synchronization. When catches the band width to change quickly causes the change, the phase-locked loop capture speed has also had the change, catches the band width to be wider quickly, the capture speed is quicker.
4 software phase-locked loop’s DSP realizes
In wide band digitization receiver’s realization, under the digit the frequency conversion uses general programmable under frequency changer HSP50214B. In realizes the carrier synchronization, in the element synchronization software phase-locked loop entire feedback loop, the numerical control oscillator, the discriminator complete by HSP50214B, the ring circuit filter complete in TMS320C6X. DSP realizes diagram as shown in Figure 7.
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The ring circuit time delay is the factor which should take seriously. Brings the software phase-locked loop ring circuit time delay mainly to have the following 2 kind of reasons:
in (1) ring circuit the FIR filter bring time delay;
(2) data waited for processing brings extra time delay.
In the digitized receiver, uses thick synchronized and the thin synchronized two levels. The thick synchronized ring circuit latency is big, the reaction rate is slow; The thin synchronized ring circuit latency is small, the reaction rate is quick, the thick synchronization guaranteed that the desired signal falls in filter’s pass band, the thin synchronization may obtain in the thick synchronized foundation catches the belt and with the ambulacrum greatly. In addition also uses abandons certain sampling points, eliminates the nonessential ring circuit time delay.
May see, the software phase-locked loop has the processing nimble merit, he got rid of the complex hardware circuit design, solved many have simulated the difficult problem which the link met. At present, because the DSP function is getting more and more formidable, the working speed is getting higher and higher, also has created the essential condition for the software phase lock technique’s development.
Reference
[1] Best R L plate hase locked loops design simulation and applications [M]. 3rd Edition completely cGraw Hill, 1997
[2] Zhang Juesheng other technology [M]. Xi’an: Xidian University Publishing house, 1994
[3] Ding jade US pen character signal processing [M]. Xi’an: Xidian University Publishing house, 1995
[4] ancestor Comte time complains about qing rate the signal processing [M]. Beijing Tsinghua University Publishing house, 1996
[5] HARRIS Corporation, The principle and application of HSP50214B
[6] John Proakis G 盌 igital communications [M]. Beijing: Electronics industry publishing house, 1999
