Abstract: To raise the low power instead to stir up switching power supply’s complete machine efficiency large scale, may select the vice-side synchronized rectification technology to substitute for the original Short base diode rectifier. It enhances one of low pressure direct-current output switch voltage-stabilized source performance most efficacious devices.
Key word: Instead stirs up the converter; Vice-side synchronized rectification controller STSR3; High efficiency converter
1 outline
This article gives switching power supply IC which ST Corporation in 2003 promoted newly the product STSR3 application circuit analysis. It instead stirs up the converter vice-side synchronization rectification controller, has the numerical control intelligent IC driver. Uses STSR3 to make the synchronized rectification control chip instead to stir up the converter basic electric circuit to simplify the structure to see Figure 1. The STSR3 internal function square see Figure 2, its pin arrangement see Figure 3.
STSR3 intelligent driver IC may provide the big electric current output, by actuates the vice-side normally power MOSFET, causes it achievement big electric current output the high efficiency instead to stir up in converter’s synchronous rectifier. According to is from the insulating transformer vice-side a synchronized clock input, IC produces a driving signal, it has with the primary side PWM signal related dead time establishment.
When primary side switch breakover, the IC work may prevent vice-side to have the error status, it provides the anticipated output closure condition. This intelligence’s function has realized fast by the week logical control mechanism, it is the establishment comes the synchronization in the high frequency oscillator by the clock pulse signal. This initialization may adjust by the IC exterior part.
After sensing examination synchronous rectifier’s source - drain electrode voltage pulse. This special forbids the function to be possible to close the actuation output, when therefore has the necessity instantly switches off it. This characteristic enables the power source to work under the non-continual breakover pattern, and avoids with the converter parallel operation synchronous rectifier reverse breakover.
The STSR3 permission switching power supply work in non-continual pattern PWM, continual pattern PWM, as well as instead stirs up the converter in the accurate resonant condition, can realize the synchronized rectification duty.
STSR3 seal as shown in Figure 3 the SO8 laminated shape part, various pins’ mark and the function outline is as follows:
Foot 1N/C, it does not meet the internal circuit;
Foot 2VCC, the power supply inputs 4~5.5V;
Foot 3SETANT, establishes the anticipated shutdown output;
Foot 4CK, is the IC work synchronized signal;
Foot 5INHIBT, meets the non-continual pattern detector;
Foot 6SGLGND, all control logic signal datum grounding;
Foot 7OUTGATE, loses the MOSFET electronics grid to actuate;
Foot 8PWRGND, power signal datum level.
Figure 4
2 STSR3 application circuit analyses
The STSR3 synchronous rectifier controller applies specifically in one kind of 90W notebook voltage-stabilized source’s actual electric circuit see Figure 4, its direct-current output is 19V,4.74A. The switching power supply is instead stirs up-like the converter, the primary side main chip uses compound PFC/PWM new product CM6805. In Figure 4 gave in detail anti- has accommodated the value. Below introduces STSR3 separately in circuit design some characteristics.
2.1 IC supplies power Vcc and the undervoltage block system output
The STSR3 Vcc power supply scope is 4~5.5V, its interior has a zener diode to limit the biggest power line voltage is 58V. Needs an external connection 100nF porcelain dielectric vessel continually in the foot 2 (Vcc) with the foot 6 (SGLGND), guarantees the stable power supply. This high frequency capacitor should abut the chip as far as possible. But met with the another 100nF porcelain dielectric vessel in the foot 2 (Vcc) and the foot 8 (PWMGND) between. The undervoltage block system input level had guaranteed the normal starting, has avoided when Vcc has been accidentally low did not hope driven operation condition. The Vcc voltage also supplies the out-port driver, therefore the biggest slaving voltage is located in 55V, therefore the recommendation uses the logical electronics grid threshold level MOSFET.
2.2 synchronous working condition
STSR3 has one kind of innovation characteristic, namely the intrinsic design enables STSR3 to work, in vice-does not have any from under the primary side synchronized signal condition. The STSR3 synchronization is from vice-side obtains directly, it uses the voltage pulse which in the synchronized switching valve MOSFET both sides exerts, transforms the transmit message as the switch. Figure 2 synchronized signal 4 (CK) inputs from the foot, the chip internal threshold level establishes in 26V. The sinusoidal waveform which in a CK input termination peak detector, after this unit electric circuit can distinguish the primary side MOSFET switch to transform induction signal as well as, appears. It causes by the non-continual pattern work or the resonant replacement shape, like Figure 5 in dead time the profile shows.
2.3 continual breakover patterns
When instead stirs up the converter work when the continual breakover pattern (CCM), has become the rectangular undulation between the synchronized MOSFET switching valve source and the drain electrode voltage pulse, as shown in Figure 6. This voltage may use two different ways to add to chip foot CK: First, with Figure 7 resistance voltage divider method; Second, a diode and holds on the resistor method with Figure 8. In majority situations, when the synchronized MOSFETA tube shuts off cuts off, in the voltage pulse profile will present a peak signal. In the chip foot CK input end, must eliminate this peak voltage first, avoids causing false synchronized triggering. When uses resistance voltage divider R1 and R2, may increase a C1 high frequency small capacitor to eliminate the peak voltage again to break out, as shown in Figure 7.
Instead stirs up the converter to use in the telecommunication a typical example, is the cocurrent input voltage has 1:2 variable scope, the typical value is 36~72V. Therefore, the vice-side winding voltage also has 1:2 variable range. Then in the 36V input time, may calculate by the differential pressure resistor in the foot CK voltage approximately is 28V; But works as when the direct-current input is 72V, then the foot CK voltage achieves 56V. Even if this value is higher than foot CK the greatest voltage is also acceptable, because it limited flowed in this foot’s electric current is 10mA.
The capacitor C1 value is decided in the synchronized MOSFET tube shuts off peak’s scope, and changes along with the R1 value. , because in order to reduce the detention which R1 and C1 both cause, uses the smallest capacitance value elected.
When uses the power source adapter instead stirs up the converter, its electrical network input working voltage is AC85~270V, its variable range is 1:3. When the electrical network input voltage is lowest, must guarantee that foot CK the voltage is 28V; Therefore when electrical network input voltage for maximum, the voltage will achieve 89V, or higher. This voltage value has surpassed the component permission maximum value. If through R1 the limit inflow foot CK magnitude of current, causes it to be lower than the foot CK permission the maximum current value, then the chip still might work normally. Otherwise, must affix diode D1, protects the chip? Damage.
Figure 8 has given holds on resistor’s synchronized circuit diagram with diode D1 and R1, does not have the shutdown peak and the foot CK overvoltage question with this kind of electric circuit. Because synchronous rectifier’s drain electrode voltage presents the ringing, therefore this electric circuit cannot under the discrete state the normal work.
Through additionally builds a NPN crystal pipe joint in foot CK and between foot SGLGND, as shown in Figure 9, and holds on resistor desynchronizing STSR3 with a diode the shutdown electric circuit, comes with Q1 and the R2 connection equivalent in the resistance bleeder chain, may shut off STSR3 easily. When Figure 9 signal “OFF” for high level, this triode breakover, forces foot CK to fall to the place level. Under this kind of condition, the OUTGATE foot will become the low level condition, thus shutdown synchronization MOSFET switching valve.
2.4 non-continual breakover patterns
Just like front shown in Figure 5, under non-continual pattern active status, when examination primary side switch change-over signal, possibly will have some problems. The chip internal peak detector, can only determine foot CK achieves peak value, but neglects other all low values the signal. Examined that Figure 5 may know, should guarantee when the switch transforms between the profile and the sine wave the smallest voltage difference is V1=400mV, can also let the peak detector work normally. In front in the direct positive narration mentioned that if the input voltage variable range is bigger than 1:2, then must increase diode D1, comes on clamp foot CK the voltage. Under this kind of condition, regardless of being the switch transforms the profile, the sinusoidal waveform by the clamp, is enabled the peak detector to work correctly, when easy to have as shown in Figure 10 the STSR3 wrong triggering the drive pulse profile. By now if used the exterior peak-detector circuit which in like chart 11 shows, can solve the problem, causes the chip can work correctly under continuously or the non-continual pattern.
2.5 exterior peak value detectors
When the input voltage variable range is higher than 1:2, available chart 11 outside peak value clock detector, front the substitution Figure 7 electric circuit, guaranteed that STSR3 correctly works under must continuously or the continual breakover pattern, it supplies the pure rectangular wave to foot CK.
R20 is one holds on the resistor, when synchronized rectification MOSFET breakover or its body diode breakover, Figure 11 V1 voltage value is the low level. When MOSFET closure (corresponds to primary side switching time), voltage V1 in the 5V value. Figure 11 R22 and C10 constitute a low pass filter, even, when the ringing pulse is zero value nearly (see Figure 12 profile), it can also have the correct synchronized signal. But, R22 and C10 will cause the delay time which did not hope, therefore, will increase R21 and the C9 combination circuit again, can when the split-second-selection will transform will reduce this detention. ST Corporation’s logical component 74V1T70 may the noise elimination, prevent it to trigger the STSR3 internal peak detector by mistake. Will give this electric circuit’s suggestion value in the following narration.
2.6 forbid the active channel
Has one kind of difference between the diode rectification and the synchronized rectification, namely when MOSFET breakover electric current possible two-way flow, but time diode breakover the electric current only assumes the single direction. When non-continual pattern with diode rectification, when inductor’s electric current falls to zero value, it cannot flow reverse, if makes the rectifier with MOSFET, when the inductance electric current falls zero, it will continue to reduce becomes the negative value, and flows to the source from the synchronized MOSFET drain electrode. Under this kind of condition, the converter probably works in the continual pattern.
If must work in the non-continual pattern, then works as the inductance electric current is the zero hour, synchronized MOSFET should cut off, therefore the body diode does uses in common the rectifier, avoids the inductance current reversal. When this electric current close 0, foot INHIBIT can shut off synchronized MOS, causes the converter work in the non-continual pattern.
The chip has met a threshold level in the foot INHIBIT interior for - the 25mV comparator. Outside this foot receives synchronized MOSFET through a resistor the drain electrode. Is starting the cut-off time (this time CK to be in low level), OUTGATE is in the high level. The INHIBIT voltage’s monitoring time is 250ns: If on the foot INHIBIT voltage is higher than - 25mV, then OUTGATE becomes the low level; If the foot INHIBIT voltage is lower than - 25mV, then OUTGATE maintains the high level, achieves - 25mV until its voltage. This is because works as when synchronized MOSFET breakover, on its drain electrode the voltage is VDS=-RDS(ON)×ID. If VDS is higher than - 25mV, this meant that the electric current is reducing, and close non-continual pattern, therefore OUTGATE shuts off, lets MOSFET the body diode work, see Figure 13. When converter when continual pattern, the foot INHIBIT voltage is always lower than - 25mV, then OUTGATE maintains the high level.
Transforms in primary side MOSFET to shutdown period, the foot INHIBIT voltage should in 250ns from Gao Jiangdao - 25mV. Chooses the R26 resistance number to suit this characteristic. When converter with other parallel connection of power source work, foot INHIBIT examination synchronization MOSFET both sides voltage, also avoids the converter from the out-port inspiration electric current.
Although foot INHIBIT permission work in non-continual pattern, but in primary side switching valve shutdown period, - the 25mV threshold level the ringing which appears to the synchronized rectification MOSFET drain electrode, possibly is sensitive, will cause the incomplete OUTGATE breakover. Provides the negative polarity voltage using the clock signal to add to foot INHIBIT to play the blanking time role, can avoid this inappropriate situation. Uses some primary devices which in Figure 14 shows, but produces this negative polarity voltage easily. The blanking time value determined by C11 and R25. It to covered the ring time conclusion is necessary, Figure 15 the line signal cut off by the primary side switch time caused. (to be continued)
