Abstract: Using Verilog HDL hardware description language design method and Quartus from the topⅡ The software, in the complex programmable logical component (FPGA, Field Programmable Gate Array) has realized the generator class frequency survey meter’s design. This design has used the electro-optical isolation technology, enhanced the system reliability and the stability. Through the simulation, indicated that this method and the conventional routes design’s digital electron system compares, is advantageous for the frequency measurement scope the expansion, simultaneously its probability is strong, the alterability is good.
Key word: FPGA; Power set; Frequency survey meter; Verilog HDL
1 introduction
Middle the modern society, the electricity resources become the people to live an essential part, but the generator and the electric motor are playing the very important role in the electrical power system. In many situations, needs carries on the survey to the electrical machinery and electrical network’s frequency. At present, frequency measurement’s circuitry are many, here introduces one kind of digital circuit frequency measurement: Based on FPGA power set’s frequency survey meter.
Develops unceasingly along with the electronic technology and progresses, as representative’s digital circuit design has the very sweeping change take EDA. In the design method, already “built tries - the welding the traditional design way from the circuit design - hardware” “the functional design - software simulation - downloading debugging” electronic automation design pattern. Under this kind of condition, (Hardware Description Language) and the logic synthesis obtains the rapidly expand take the hardware description language as the foundation electron design method from the top. Verilog the HDL language applies the most widespread hardware description language at present, it is develops in the C language foundation, the grammar is more free nimbly, has the widespread study community, the resources to be quite rich, and easy to study simply easy to understand. This article generator class frequency survey meter’s design is language foundation launches in Verilog in the hdl, source program after Altera Corporation’s QuartusⅡ5.0 softwares have completed the synthesis, the simulation (function simulation and succession simulation), FPGA (Field Programmable Gate Array, what the scene programmable gate array) selects is Cyclone the series EP1C3T144C6 component.
2 frequency measurement electric circuit
2.1 frequency measurement overall electric circuit
Uses the voltage transformer to bring from the power set terminal voltage or the network voltage frequency measurement input signal, after clipping, filter processing, turns the scope basic invariable stable profile, after the amplifying circuit the signal enlargement reshaping, will use the voltage comparator to have again the positive and negative peak-to-peak value square-wave to turn only then the peak-to-peak value square-wave signal. Then, causes FPGA through the electro-optical coupler the number system and the input signal isolates. The FPGA number system after isolating the square-wave signal pulse integer carries on the counting using the standard 1HZ signal, obtains the signal frequency number, this frequency number after nixietube demonstration. Because power set’s frequency and the power set terminal voltage has the relations, may obtain the power set terminal voltage’s change from the frequency change. From system overall diagram as shown in Figure 1, may see, this FPGA number system and the input channel isolate, thus sharpened system hardware’s antijamming ability greatly.
Figure 1 system overall diagram
2.2 frequency measurement principle
Frequency measurement’s principle is calculates each second testing signal the pulse integer, is also (cycle is 1s) the pulse width signal carries on the counting using standard 1HZ to the input testing signal pulse, after 1 second counting had ended, to gathers the pulse integer to deliver the nixietube demonstration.
The frequency measurement controller has 3 input signals: Samplefreq is the standard signal impulse, Reset is the reset direct signal, Start starts the measuring signal; 3 output signals: Endmeasure was finishes the measuring signal (counting to reposition and to transform replacement), Gate was permits the counting signal (i.e. gating signal), Enableconvert starts the change-over signal. The control flow is repositions first to the frequency meter, then starts to survey, in the Samplefreq signal’s rise along, the Gate signal enables to make the counter to start to work, to the Samplefreq next rise along, Gate reverses the low level to cause the counter stop counting, simultaneously Enableconvert makes the switch to start to transform the binary number (switching time to be lower than 1s). After the transformation had ended, the decimal digit undergoes 7 section of demonstration decoder decoding, then in the nixietube demonstrated that measures the signal the frequency. Because the Enableconvert signal’s use causes the nixietube data demonstration to be stable, will not present the twinkle. Before carrying on the next time survey, must carry on the replacement to the frequency meter, causes the nixietube the digital demonstration reset, prepares for the next time demonstration.
This article designs the digital frequency meter has six module compositions: Frequency measurement control module (Control), ten frequency division module (divfreq), binary counter module (Counter), latch module (Latch), binary system to decimal base’s switch module (Bit2Bcd), 7 section of demonstration decoder module (Led_encoder).
3 frequency survey meter’s design
This design uses Verilog the HDL language, the utilization design idea from the top. Will be systematic according to the function according to the level decompose, first defines the top layer functional module, and has carried on the description in the top layer functional module internal connection relations and the foreign connection relations, but the function block’s logical function and realizes the form to describe specifically by the next module. The entire design is divided two steps: First step uses Quartus Ⅱ5.0 graph block input mode design top layer module, top layer graph block as shown in Figure 2; Second step in the top layer module for each graph block production hardware description language (Verilog HDL), then in production Verilog in the HDL design document, carries on the description design to the underlying bed functional module’s function.
Figure 2 top layer graph block
3.1 frequency measurement control module design
This is three inputs three output modules, the frequency measurement control module profile imitates eternal truth shown in Figure 3, if uses Verilog the HDL description is:
module Control (clk, reset, start, enableconvert, gate, endmeasure);
input reset, start, clk;
output enableconvert, gate, endmeasure;
reg enableconvert, gate, endmeasure;
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
endmeasure <= 1 ‘ b1;
enableconvert <=1′b0;
gate <= 1 ‘ b0;
end
else
begin
endmeasure <= 1 ‘ b0;
if (start)
begin
gate <= ~gate;
enableconvert <= gate;
end
end
end
endmodule
Figure 3 frequency measurement controller profile simulation succession chart
3.2 binary systems to decimal base’s switch module design
This design, needs to transform the clock Convertfreq signal to carry on the sequential control to the transformation module, because must complete the transformation in 1s, then the transformation clock Convertfreq frequency should select the high repeatedly signal, namely the transformation clock Convertfreq frequency is the standard clock Samplefreq signal 10 frequency divisions obtains.
To carry on the profile simulation to this design, takes the input 10 binary number bin [9..0] is 10 ‘ b0000011001 (decimal base is 25). Figure 4 is the binary system to decimal base’s switch’s simulation succession chart:
Figure 4 binary system to decimal base’s switch’s simulation succession chart
4 simulations and debugging
Through the above description, has carried on the simulation from each module independent angle to it, finally indicated that the design meets the requirement. For guarantee system’s overall reliability, made the simulation to the overall system, simulation succession chart as shown in Figure 5:
Figure 5 system simulation succession chart
And, LEDD, LEDC, LEDB, LEDA is the decoding result must demonstrate on 7 sections of nixietubes that 0010010 (demonstration is 2), 0100100 (demonstration is 5).
Will design the frequency survey meter downloads to goal chip EP1C3T144C6, and analog simulation which carries on the GW48 experiment box, when the input frequency is 1 Hz~1023 Hz signal, the frequency survey meter measured the frequency is completely accurate, when the frequency is higher than 1023Hz, the system reports to the police, simultaneously the frequency demonstration is 0.
5 concluding remark
Based on the FPGA design’s generator class frequency survey meter, the system selects the electro-optical coupler’s isolation method in the whole, sharpens system’s antijamming ability and the stability. This system has the line simply reliable, the versatility to be strong, stability higher merit, but widely applies in the frequency voltage changer, the rotational speed relay.
This design’s FPGA number system part uses Verilog the HDL language, gives the kernel program, and may language comprehensive tool carry on the corresponding hardware circuit’s production through Verilog the HDL, has superiority which the traditional logic design method is unable to compare. After process simulation, the confirmation design is successful, achieves the anticipated result. Simultaneously this methods design’s digital electron system probability is strong, the alterability is good. If needs the frequency measurement scope needs to expand, does not need the hardware change only to change the software to be possible.
Reference
[1] Zhang Ming. Verilog HDL practical course [M]. Chengdu: University of Electronic Science and Technology of China publishing house, 1999.
[2] Chen Xinhua, Jiang Xiaohui, Zhang Jianli and so on. Designs [J] based on the FPGA digital signal display system software and hardware. Micro computer information, 2004,12:110~111.
no matter what [3] likes the front, at the beginning of the Xiu qin, being everlasting and so on. Designs [M] based on the FPGA embedded system. Xi’an: Xidian University Publishing house, 2004.
[4] Zhao Xicai. Isolates the amplifier and applies [J]. Applications of Electronic Technique, 2000,3:70~72.
