Abstract: The present paper mainly discussed and the simulation based on the CPLD PSK system unit design, during elaboration modulation demodulation system’s basic principle and design method, also introduced in detail system’s overall electric circuit diagram and each module’s concrete software and hardware realized. The author takes the design by VHDL the hardware description language, in Altera Corporation’s Maxplus2 developed in the platform to carry on the programming and the profile simulation. is this design main characteristic “from the top”, all procedures passed have taken the main chip by EPM7128SLC84-7 the CPLD experiment to develop the board the hardware debug.
Key word: Modulation demodulation, CPLD, VHDL
1 introduction
The Communications Today system request signal distance is far, the message capacity is big, the transmission quality is good. Of a modulation demodulation technology as its key technologies has been important direction [5] which the people study. From the analog modulation to the digital modulation, develops from the binary system to the multiple system modulation, although the modulation system are many and varied, but is toward causes the communications system to be higher speed, a more reliable direction to develop. A system’s correspondence quality, relies on to a great extent the modulation system which uses. Therefore, to modulation system’s research, will be deciding communications system quality quality [1] directly.
The complex programmable logical component (CPLD) unified the specific IC and the DSP superiority, both has the very high processing speed, and has certain flexibility. Therefore, has the vital practical significance based on the CPLD digital modulation system’s research. How did this article elaborate has used CPLD to realize the PSK digital modulation system’s method, it realized the step to include: 1. studies the PSK modulation system’s principle and the design method; 2. acts according to each system’s overall function and the hardware characteristic, the design overall diagram; 3. according to the VHDL language feature, carries on the VHDL modelling to the system; 4. according to the VHDL model, carries on the concrete VHDL language programming; 5. the pair of design’s procedures carry on the profile simulation and the hardware debug.
2 modulation demodulation system’s principle
Carries when baseband signal’s high frequency sine wave signal is called the carrier, in mathematics the accurate expression sine wave, frequently uses oscillation amplitude A, the angular frequency and the phase three essential factors, namely
y(t)=A cos (t ) (2-1)
According to baseband signal’s value, changes in three essential factors any kind, had 3 basic modulation systems: The digital signal is called the amplitude shift keying to the carrier amplitude modulation, namely ASK (Amplitude Shift Keying); Is called the frequency-shift keying to the carrier frequency modulation, namely FSK (Frequency Shift Keying) [3]; Is called the phase-shift keying to the carrier phase modulation (phase keying), namely PSK (Phase Shift Keying) [2].
Because the PSK system anti-noise performance surpasses ASK and FSK, moreover the frequency band use factor is high, therefore, in the high speed figure correspondence is widely used.
This article only elaborates [4] to the PSK modulation system.
3 system’s overall concept designs
3.1 CPSK system designs
CPSK by the transmitting end modulation module and receiving end’s demodulation module constitution, its system diagram as shown in Figure 3-1. In the transmitting end, regarding the modulation module, first produces two kind of different phase intelligence signal f1 and f2, two chooses a gating switch through one to choose the intelligence signal again, the concrete intelligence signal decided by the input baseband signal. These signal processing realizes in CPLD, the output is the CPSK modulation signal, finally transmits the receiving end through the channel. Regarding the demodulation module, the modulation signal first by the position synchronization extraction circuit extraction carrier synchronization signal, then by the carrier synchronization signal control counter’s start and the stop, counts separately to the modulation signal, finally judges the input through a decision electric circuit the modulation signal is `0 ‘ `1 ‘, output namely for demodulation baseband signal.
Figure 3-1 BCPSK system diagram
3.2 DPSK system designs
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Figure 3-2 BDPSK system diagram |
The DPSK signal application are many, but because its modulation rule is quite complex, produces directly with difficulty, at present the DPSK signal’s production many uses the code transformation to add the CPSK modulation to obtain. After this method is conveys a message the anlage the number process basic code - - relative code transformation, with the relative code carries on the CPSK modulation, its output is the DPSK signal. Similarly, regarding DPSK signal demodulation, then must undergo the relative code - - basic code transformation. Its system diagram as shown in Figure 3-2.
4 design based on the VHDL PSK system circuit and realizes
4.1 2CPSK modulation module
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Figure 4-1 2CPSK modulation module VHDL model block diagram |
2CPSK modulation module’s VHDL model block diagram as shown in Figure 4-1, its model mainly and two chooses a switch by the counter and so on to be composed. The counter carries on the frequency division and the counting to the external clock signal, and outputs two group phase opposite digit intelligence signal; Two choose a switch’s function is: Under baseband signal’s control, carries on the selection to two group intelligence signals, the output signal is the CPSK signal. In chart not including analogous circuit part, output signal for digital signal.
Its profile simulation chart as shown in Figure 4-2. And intelligence signal f1, f2 are obtain through the system clock clk frequency division, and lags a system clock clk cycle; Modulation output signal y a lag carrier clk cycle, lag system clock 2 clk cycles.
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Figure 4-2 2CPSK modulation module profile simulation chart |
4.2 2CPSK demodulation module
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Figure 4-3 2CPSK mediation module VHDL model block diagram |
2CPSK demodulation module’s VHDL model block diagram as shown in Figure 4-3. In the chart counter q output and the start synchronization 0 approach the digital carrier. The decision principle of work is: Carries on logic the counter output’s 0 carriers and in the digital CPSK signal’s carrier “and” the operation, when two comparison signals when the decision time is “1″, the output is “1″, otherwise the output is “0″, realizes the demodulation goal. In the chart has not contained the analogous circuit part, the modulation signal for the digital signal.
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Figure 4-4 2CPSK mediation module profile simulation chart |
Its profile simulation chart as shown in Figure 4-4. When q=0, carries on according to x level to the phase the decision; And output signal y a lag input signal x clk cycle.
4.3 basic code - relative code transformation module
Between the basic code - - relative code’s relations are
(type 4-1)
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Figure 4-5 basic code - relative code transformation module VHDL model block diagram |
From this, may obtain the basic code - relative code transformation module VHDL model block diagram, as shown in Figure 4-5. In the chart counter and Figure 4-3 counter is the same, the different or gate and the register complete together/transform the function certainly.
Relative code - basic code transformation module with this similar, here does not perform to elaborate.
5 system debugging summary
This topic studied and traced the correspondence domain and the EDA design domain two key technologies - - modulation demodulation technology and the programmable logical technology, all project work was in the CPLD experiment developed on the board to complete together, has selected the Altera Corporation model is EPM7128SLC84-7 takes the main chip. And the input signal provides by the monolithic integrated circuit, after undergoing the CPLD processing, output signal’s profile may observe [6] through the oscilloscope. But because the modulation system and the demodulation system’s test is carries on separately, will not have intuitive like this inevitably, and has not been able to consider in the actual system does not decide the factor. But above these, will be this design must further improve and the development place in the future.
Paper innovation spot: The paper selects the top-down development method, (CPLD) designs through the complex programmable logical component realizes the modulation demodulation system, by direct enhancement communications system quality.
Reference
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[3] Xu is bright, Xu Feng. 2FSK signal producer’s FPGA designs [J]. Beijing: Modern electronic technology, 2005,10 (22): 60-61
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[5] Chen Zhibin, Zhuo Jiajing. Designs the [J]. micro computer information based on the monolithic integrated circuit and the CPLD embedded pulse generator, 2005,2
[6] Fuqin xiong, Modern Techniques in Satellite Communications, IEEE Communications Magazine,1994,(8):17-20
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