1 introduction
As a result of the FPGA appearance, caused us not to need to undertake the big risk and the high class piece expense or is in the small scale the research and development stage the chip to make the ASIC chip. But based on FPGA SOC–SOPC (on programmable piece system), because its programmable, specific needs to construct according to the user SOPC is one substitutes SOC to a certain extent the good plan. Altera Corporation has developed second generation of soft nucleus embedded processor NiosII for its FPGA, the simultaneous development has used to construct based on NiosII processor’s SOPC Builder, causes the user to be possible through to develop conveniently from the definition logic method based on the NiosII SOPC system. SOPC the Builder integration in EDA in tool QuartusII, has provided the NiosII processor and some commonly used peripheral device connection, like the DMA controller, the SDRAM controller, SPI connection as well as phase-locked loop PLL and so on, the module users who has not provided regarding some storehouses in may define the increase. In the practical application, had I2C connection EEPROM to have the widespread utilization, this article is in has designed EEPROM Controller Core based on NiosII SOPC, with Verilog the HDL description hardware logical gate, simultaneously compiled the related actuation, downloaded has realized to Stratix series FPGA to the piece outside EEPROM A
T24C02 read-write.
2 based on NiosII Controller Core
In SOPC various modules the Avalon main line interconnection which develops through Altera Corporation. Any hangs meets must conform to the Avalon main line standard on the Avalon main line’s module, namely contains specific signal type clk, reset, chipselect, write, writedata and so on, and satisfies certain establishment maintains the time and the waiting cycle read-write pattern. Typical module’s Controller Core and actuates the software two parts of constitutions by the hardware.
2.1 hardware constitutions
Is uses in based on NiosII Controller Core constructing SOPC the basic module, it describes its hardware logic by the HDL language, typical Controller Core by task logic (behavior module), register file (register), interface (bus interface) three parts is composed, they in logic incidence relation as shown in Figure 1:
Chart 1Controller Core in logical incidence relation
interface is the top layer module, with Avalon main line’s direct connection; register file: Connection module, to module interior register read-write channel; task logic: The behavior module, realizes the module logical function hard core. The Avalon main line carries on the operation through the top layer interface module to the register, thus realizes visit to behavior module and the control.
2.2 actuate the software
Actuates the software is the system provides for the upper formation application procedure visits the first floor hardware’s channel, is composed of some specific name’s folder and the C document, its modular design and the function are as follows:
(1) a inc/_regs.h document is the lowest level is also the only hardware interface, has defined with Controller the Core related construction of data, the constant and the function primary form and so on.
(2) a hal/inc/_routines.h document contained has realized the actuation function function statement and so on related information.
(3) the hal/src/_routines.c demonstration procedure contained has realized the actuation function sub-function specifically, used in instructing the software developers to use this Controller Core.
3 EEPROM principle of work
Two-wire system EEPROM AT24C02 is one kind uses the I2C connection serial to be possible the electricity to clean the programmable non-erasable storage. Because its wiring is simple, and has the enough flexibility to the data revision, therefore obtained the widespread application.
3.1 I2C main line standard
The I2C main line is by data line SDA and the clock line SCL constitution, may transmit and receive the data. The I2C main line altogether has three fundamental type signals in the transmission data’s process, they respectively are start the signal: When SCL is the high level, SDA by the high level to the low level jump, starts to transmit the data. Conclusion signal: When SCL is the high level, SDA jumps by the low level to the high level, conclusion transmission data. Answering signal: The receiving end in receives after 8 bit data, must to the transmitting end send out the specific low level pulse, expressed already receives the data.
3.2 two-wire system EEPROM principle of work
May carry on the read-write operation based on NiosII SOPC through EEPROM Controller Core to it, the read-write rule must follow EEPROM the succession request.
(1) EEPROM writes the operation
As shown in Figure 2, after EEPROM Controller sends out “the start” the signal, follows closely is transmitting 4 I2C main line condition code 1010, xxx as well as writes status byte R/W=0 with 3 chip addresses. After treating receives outside the piece component’s answering signal ACK, the controller with will be transmitting the data which the EEPROM memory cell address and must read. EEPROM receives a byte every time the data, must transmit a ACK answering signal returns to give the main engine. Afterward the main engine transmission stop signal, writes a byte to EEPROM the operation to complete. 
(2) EEPROM reads the operation
As shown in Figure 3, EEPROM reads the operation including to write the address and to read the data two steps. The controller first transmits one “the start” the signal and the control byte (including component address and read-write status byte R/W=0) arrives at EEPROM, through writes the operation to establish the EEPROM memory cell address. Then the controller again transmits one “the start” the signal and the control byte (this time R/W=1), the start reads the operation, after EEPROM receives the information, will assign the unit the data to transmit to SDA on-line, after the controller receives the data, returns to a NACK signal to give EEPROM, afterward transmits the stop signal.
4 EEPROM Controller Core design
4. 1 hardware part design
(1) task logic design
This design’s task the logic behavior module is based on NiosII EEPROM the Controller logical function hard core, must realize through the NiosII system carries on the read-write to EEPROM, must defer to the I2C main line standard and the EEPROM read-write request designs Controller Core. The limited state machine is the way which in the sequence circuit design uses frequently, is many digital circuit design core. Therefore, we use the state machine to realize controller’s core logical gate. May know according to the serial EEPROM read-write operation succession, may complete with 5 condition clocks writes the operation, may complete with 7 condition clocks reads the operation. In the read-write condition has several conditions is consistent, with a nesting state machine then. Condition shift chart as shown in Figure 4.
Figure 4 condition shift chart
(2) register file design
register file in fact is the NiosII processor carries on and the control channel through the software visit to the hardware, it is composed of a series of registers, and had stipulated how to carry on the read-write to it. In the Register file register is the specific logical function which needs to complete according to task logic in establishes, in task logic data through register file in register transmission. In this design, in register file has established the control word, the address and data-carrier storage ctrl_reg, addr_reg, wr_reg, reads data-carrier storage rd_reg, its width is 8.
(3) Interface design
The Interface interface module is with Avalon a bus interface top top layer module, the major function is module and register the file module carries on the example to task the logic and the seal, causes its input/output signal to conform to the Avalon main line signal standard completely, with external connection module signal standard. In this design, with the Avalon bus interface’s signal is: clk, resetn, avalon_chip_select, address, read, write, write_data, read_data; With the external connection EEPROM connection’s signal is: sda, scl.
Like Figure 5 is EEPROM Controller Core the hardware part design modelsim simulation chart, according to the component rule, simulates the Avalon total terminal to write the control word, the address and the data register continuously, the content which the Controller module basis writes transmits the data to SDA on-line, realizes to the EEPROM read-write.
Figure 5 EEPROM Controller Core hardware part design modelsim simulation chart
4. 2 software part design
After the EEPROM controller core hardware part designs, but also needs to compile the related driver only then to be able to increase to SOPC in uses. Its actuation design is as follows:
(1) in inc altera_avalon_ eeprom a _regs.h document the system read-write function which provides according to NiosII, has defined the read-write register’s function prototype, as follows shows:
#define IOWR_ALTERA_AVALON_EEPROM_CTRL_WRITE (base, data) IOWR (base, 0, data)
#define IORD_ALTERA_AVALON_EEPROM_DATA_READ(base) IORD (base, 4)
(2) in the src altera_avalon_eeprom_routines.c document, the primary function which defines to altera_avalon_eeprom_regs.h in carries on the transfer, compiled has realized to the EEPROM random address read-write data function, wrote the function the code to be as follows:
void altera_avalon_eeprom_write (unsigned int address, alt_u8 ctrl_write, alt_u8 addr_write, alt_u8 data_write)
{
IOWR_ALTERA_AVALON_EEPROM_CTRL_WRITE (address, ctrl_write);
IOWR_ALTERA_AVALON_EEPROM_ADDR_WRITE (address, addr_write);
IOWR_ALTERA_AVALON_EEPROM_DATA_WRITE (address, data_write);
}
5 EEPROM Controller Core increase
First, increase designs good Controller Core with in SOPC Builder new component the edit, increases as shown in Figure the HDL language description’s document and the actuation software 6, and according to Avalon main line transmission standard establishment related holding wire and transmission parameter. After completing, may increase Controller Core to the SOPC project, and downloads its translation to the FPGA component.
Figure 6 the HDL language description’s document and the actuation software increase
At the same time, in NiosII in the IDE environment, we may compile the user application procedure, uses component which one increase. Here, we transferred the altera_avalon_eeprom_routines.c definition the function to compile the simple test order, to the EEPROM goal place
The site write data and from this address the data read-out, reads out in the console control bench the result to be correct.
6 conclusions
This article designed based on NiosII EEPROM Controller Core, the design has included the HDL language description hardware part and the software driver, and increased Controller Core to the SOPC Builder storehouse, finally downloaded to Stratix1S10 FPGA on, has carried on the confirmation through the read-write function to it. At the same time, this design also to develop other to provide a model based on SOPC Controller Core.
