Abstract: Uses the FPGA scene programmable component to realize the VRLA accumulator cell test system’s complex data gathering electric circuit, the USB data communication interface, the register electric circuit, the overstep alarm circuit and so on essential module design, the data acquisition electric circuit module substitutes the double knife type relay analog switch with the differential type analog switch electric circuit, the overall construction used FPGA to program, the encryption nimbly good, the design production cost low status merit, its firmware development’s data acquisition electric circuit was higher than the conventional gathering card stability, the systems operation performance was good.
Key word: Scene programmable gate array; VRLA accumulator cell; Differential type analog switch; VHDL language
1st, introduction
The valve will control the type lead-acid battery (VRLA) to present the battery container in the actual use to distort, the electrolyte leakage, the capacity insufficiency, the battery terminal voltage non-uniform and so on phenomena, the practice proved that the entire group battery’s capacity will be take the condition worst that battery’s capacity value as a standard, but will not be take the mean value or the rated value (starting value) as the standard, when battery’s actual capacity will drop to below itself rated capacity 90%, the battery will then enter the winter, when the battery capacity will drop to original 80% below, the battery will then enter the sudden decline condition, the winter is very short, this time the battery has had the enormous accident potential, will therefore be rightThe VRLA accumulator cell’s examination and the online monitor fixed time are very important and must.
2nd, hardware circuit design
The VRLA accumulator cell online observation system major function is each VRLA accumulator cell’s terminal voltage carries on to the direct-current power supply VRLA battery unit in inspects, its working divides into the real-time monitor and fixed time monitors two kinds, fixed time monitors the time-gap by the user according to the actual need hypothesis, the user may momentarily cut real-time with fixed time monitors two kind of working patterns, through the monitoring device demonstrated that the voltage, the temperature, the internal drag curve realize to single and the whole VRLA accumulator cell’s monitoring operation. May complete the graph printing, the graph preservation, the curve demonstrated that the historical data playbacking many kinds of management functions, and the default establishment overstep warning voltage and the temperature range limits, if has the unusual circumstance to send out the alarm immediately.
2.1 test system hardware architecture
This example FPGA development system uses Xilinx the FPGA control module Spartan-II(XC2S200), differential type multi-channel analog switches (including analog switch CD4051 and optical coupler TLP181), A/D transforms the AD0809 chip, Philips Corporation PDIUSBD12 general serial interface chip, Winbond Corporation W29C020C and the mouth Flash memory and SRAM W24257, 2×4 constitutions and so on keyboard array, overstep warning component. The ideal VRLA accumulator cell test system, through real-time monitors in the VRLA battery unit the single-node VRLA accumulator cell’s voltage, the interface resistance and the temperature can the effective recognition single-node VRLA accumulator cell’s performance difference and the security critical point, active control single-node VRLA accumulator cell excessively sufficient, has put hotly with out of control, realizes the balanced electric discharge and the equalizing charge ideal function; Simultaneously calculates the single VRLA accumulator cell electric quantity accurately, according to the charging and discharging curve, establishes the best charging and discharging method, and with the controller intellectualization coordination, determined that the VRLA accumulator cell load characteristics parameter choice, lengthens the VRLA accumulator cell service life.
Figure 1 complete machine system diagram
2.2 differential type multi-channel analog switch design
The relay which the data acquisition circuit design uses the differential type multi-channel analog switches to be possible to avoid the conventional double knife type relay analog switch to large-scale VRLA battery unit survey when needs being too many, instrument’s volume is oversized, the power loss, the cost and the failure rate higher numerous shortcoming, like the graphical representation differential type analog switch work power source by measured that the VRLA battery unit provides, and uses the optical coupler isolation sampling switch and the low-voltage system, solves the VRLA battery unit battery number to be many, the voltage is high, surveys and so on questions with difficulty. The differential type analog switch work process is: The FPGA controller carries CA, CB through the control simultaneously to control U1, U2 eight to choose an analog switch, if the control end simultaneously selects input end B1, then analog switch U1 out-port OUT1 outputs VRLA accumulator cell B1 the terminal voltage, but analog switch U2 out-port OUT2 loses the origin is B1 negative terminal voltage, if receives OUT2 measurement system’s place level, OUT1 receives the measurement system signal input end, is then observable VRLA the accumulator cell B1 each data value. So long as likewise, controls CA, CB to be possible to complete to the B1~B4 each monomer battery data gauging, subsequently obtains the entire group battery’s each parameter data.
Figure 2 differential type analog switch electric circuit schematic diagram
3rd, software design
The system software uses the modular design, the first floor firmware program is composed of the VHDL language programming certain subroutine block, including host The control procedure, the data acquisition subroutine, ultra limits the judgment and the warning subroutine, the USB vertex correspondence subroutine, the interrupt processing subroutine; The superior machine application procedure environment develops in Visual under the Basic, may complete the graph printing, the graph preservation, the curve demonstrated that management functions and so on historical data playbacking.
3.1 master control procedures
Uses in completing FPGA and the external module on electricity self-checking and the initialization, the initialization flash memory, the SRAM work area, a/D switch and the differential motion analog sampling channel establishment, the USB port and the peripheral connection on electricity replacement. The initialization will give the hypothesis to the original state, including timer, interrupt opening and so on. And the external interrupt uses in responding operations and so on keyboard signal and USB mouth interrupt response and superior machine correspondence.
3.2 USB control vertex interrupt service flow chart
The USB control vertex interrupt service function is after USB passes sends out the interrupt response unguardedly current designation single-node data and so on accumulator cell’s voltage, temperature stores the corresponding data area, for the system demonstrated that functions and so on warning, correspondence provide the primary data, afterward acts according to the user establishment the accumulator cell number of classes, each group of accumulator cell pitch number and the hypothesis voltage, the temperature value, makes the corresponding revision the primary data then in the superior machine application procedure place demonstration each group of accumulator cell’s single-node battery voltage and the overall accumulator cell’s voltage, the temperature, the internal drag curve.
Figure 3 USB control vertex interrupt service flow chart
3.3 USB control vertex correspondence establishment initialization routine
Refers to Philips Corporation PDIUSBD12 data book, the PDIUSBD12 order character divides into three kinds: The initialization order character, the data stream order character and the general order character, FPGA gives PDIUSBD12 the order address to send the order first, transmits or the read-out different data again according to the different order’s request. Therefore, may make each kind of order the function, realizes each order with the function, later direct transfer correlation function then. FPGA internal USB control vertex and PDIUSBD12 correspondence initialization routine detailed list:
constant D12_CONNECT_DATA: REG8×8:= // disposes the order and the data
(D12_COMMAND_SET_DMA, // establishes the DMA order
D12_DMA, // routing directive data
D12_COMMAND_SET_MODE, // transfer system pattern order
D12_MODE_CONFIG, // transmission pattern establishment
D12_MODE_CLOCK_DIV, // transmission frequency division rate pattern
others => X ” 00 “);
constant D12_CONNECT_DATA_TYPE: REG8×1:= // orders, the data execution sequence
(D12_COMMAND,
D12_DATA, // transmission data
D12_COMMAND,
D12_DATA, // transmission data
others => ‘0′);
constant D12_CONNECT_DATA_LENGTH: INTEGER8: = 5; // disposition parameter total length
constant D12_EP0_ACK_DATA: REG8×8:= // disposes 0 breakpoint commands
( D12_COMMAND_SEL_EP0_OUT, // transmits 0 break point choices
D12_COMMAND_ACK_SETUP, // confirms the establishment
D12_COMMAND_CLEAR_EP_BUFFER, // clear register
D12_COMMAND_SEL_EP0_, // receives 0 break point choices
D12_COMMAND_ACK_SETUP, // confirms the establishment
others => X ” 00 “);
constant D12_EP0_ACK_DATA_LENGTH: INTEGER8: = 5; // disposes 0 break point total lengths
constant ep0_ack_data: REG8×8: = D12_EP0_ACK_DATA; // transmits 0 break point data
4th, conclusion
Is flexible based on the FPGA VRLA accumulator cell test system full use firmware programming debugging, the development cost is low, on the piece superiority and so on fruitful in resources, can facilitate realize many groups to input the simulation quantity the expansion. May realize to monomer voltage 0~15V, entire group voltage 0~500V, the voltage measurement precision: ±0.5%; Temperature survey scope: - 20℃~ 80℃; Interface resistance test scope: 0~99mΩ and so on high precision parameter survey.
Reference:
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[2]. Zhou Zhimin, Zhou Jihai the valve controls the type seal lead-acid battery operative technology [M] China Electric power Publishing house 2004.10,97-109
[3]. Wan Lifeng based on PDIUSBD12 USB data acquisition system’s design [J] micro computer information 2006.5-1,110-112
[4]. Zhou Shenghai integrates the multi-channel analog switch’s application skill [J] Applications of Electronic Technique 2005.7,79-80
[5]. PDIUSBD12 USB Interface Device datasheet Ver.08 Philips Co., 2001
