Abstract: In the article proposed one kind of DS/CDMA wide frequency modulation and the despread demodulation system model, has analyzed this model wide frequency modulation principle and the despread demodulation principle, with was designing has used in realizing the despread demodulation module radio frequency circuit and the digital baseband processing electric circuit diagram, has analyzed their composition and the work process, used in the component as well as the design used the essential module showed in detail, finally introduced this despread demodulation module application domain as well as the actual use effect.
Key word: DS/CDMA; Code piece speed; AFC; DDS; FPGA
In the CDMA communications system, uses in the base depot signal repeater the receiver is a nucleus module, a receiver is only processes a group user the despread demodulation is obviously unreasonable, to raise receiver’s efficiency and reduce the cost, it is necessary to design one kind of multi-channel CDMA signal general despread to demodulate the platform. But FPGA has the function to be formidable, the development engineering investment is small, the cycle is short, may program repeatedly revises, keeps secret the performance to be good, merits and so on development kit intellectualization, this project decided that uses the FPGA achievement to design the platform; This article has first established the CDMA signal wide frequency modulation and the despread demodulation system model, then proposed that designs this kind of multi-channel CDMA signal general despread to demodulate the platform. This platform will guarantee that processes the CDMA despread demodulation the versatility, may also use this platform in the CDMA signal honeycomb base depot construction, may also use, in the CDMA satellite ground’s base depot constructs on.
Figure 1 DS/CDMA despread demodulation system principle diagram
1 DS/CDMA signal despread demodulation system model
According to internationally the DS/CDMA signal development’s present situation, we hoped that designs one to be possible to carry on the despread demodulation to the DS/CDMA signal the general platform, this platform’s system model as shown in Figure 1:
Analyzes this system model, in does not consider the noise and in the disturbance situation, this system’s input signal =, after orthogonal under frequency conversion to baseband:
Each related operation item records separately the above equation in does:
2 design CDMA based on FPGA the despread demodulation process wireless SOC to develop platform 499 Yuan S3C4
The equipment realizes the key technologies foundation which realizes based on third generation mobile communication system, uses large-scale FPGA the hardware platform which realizes as the equipment, may take the direct sequence spread spectrum/code division multiple access signal receive the general processing platform. Draws up the CDMA despread demodulation module overall concept diagram as shown in Figure 2.1.
Intermediate frequency AGC unit control 70MHz intermediate frequency input signal input energy, after the component AD6640 sampling sends in the FPGA signal processing module to carry on under the digit the frequency conversion to the I/Q road baseband, conveys a message the I/Q roadbed the number to send in again the parallel detection module to carry on the user examination; The parallel detection module uses large-scale programmable logical component ALTERA Corporation’s EP2C70F672 to realize, is mainly completes in the hunting zone through the parallel matched filter the PN code, the PN code which examines is fed back again sends in the FPGA signal processing module to carry on despread demodulation processing. The FPGA signal processing module uses ALTERA Corporation’s EP2S60F672 to realize, this part is composed of 16 modules, each module may complete functions and so on address capture and track, related despread, phase estimate, baseband demodulation, outputs the Viterbi soft decision data signal; The master control unit also designs in EP2S60F672 realizes, this unit completes functions and so on DDS control, ADC sampling frequency disposition, carrier frequency initialization disposition, address disposition, active status examination, each kind of disposition and the examination information use the computer control input through the network interface. Wireless SOC develops platform 499 Yuan S3C44B0 ARM7 development board 378 Yuan S3C2410 ARM9 development board 780 Yuan AT91SAM7S64 ARM7
Figure 2 CDMA signal receiving apparatus overall concept diagram
3 several essential modules realize the process
Intermediate frequency processing and the ADC unit mainly by the intermediate frequency automatic gain control, the bandpass/low-pass filtering, the DDS sampling clock generator, intermediate frequency ADC sampling these modules is composed, uses the speed is the code piece clock N time of clock takes the sampling clock, after then sends in the sampling data in FPGA.
The baseband receive processing unit by the digital orthogonal under the frequency conversion, clock datum DDS, the controllable address has, the multi-channel parallel address search capture, the digital interpolation code piece track, the code channel to estimate that (scope, phase estimated that the SIR estimate), the multi-channel data correlation despread, the difference demodulation data interface (does not restore these parts including data frame) to compose, mainly completes the signal the receive despread demodulation function.
The master control unit mainly by the initialization disposition (carrier frequency disposition, address disposition, active status disposition), the active status examination (capture instruction, synchronization indication, accepting state and so on), control interface processing (network interface), modules and so on RS-232 connection is composed. The MCU main line and the baseband processing unit is connected, uses in the parameter disposition control, active status functions and so on information acquisition and demonstration, external communication; The network interface mainly completes the hardware and computer’s data exchange; RS-232 connection primary control liquid crystal demonstration as well as keyboard entry.
Concluding remark: Based on the DS/CDMA signal despread demodulation’s basic principle, unifies large-scale logical component FPGA the merit, this article author innovates proposed that designs an general despread to demodulate the platform, this platform already may use in the CDMA signal honeycomb base depot receiver’s nucleus module, may also use in the satellite CDMA signal the despread demodulation; This platform already obtained the application and the confirmation on the base depot receiver, the practice proved that this module search speed is quick, simultaneously the despread demodulation’s number of users achieved 16, the despread demodulation efficiency has been extremely high. Because this module uses ALTERA Corporation’s large-scale FPGA component, therefore very easy to transform uses in the ASIC electric circuit, has the very broad application value.
Reference:
[1]Altera the FPGA/CPLD design (high-level), Wu Jihua, the king is honest, people’s posts and telecommunications publishing house, in July, 2005
the [2] wide frequency correspondence digital baseband signal processing algorithm and VLSI realize, open joyful, the Scientific Publishing house, in August, 2004
[3]Koji Ohno, Mamoru Sa Sawahashi, and Fumiyuki Adachi, “Wideband coherent DS-CDMA”, Proceedings of the 45th EEE VTC Conference, Chicago, pp 779-783,1995.
[4] Yang Kuiwu, Wei Bo. In the wide frequency correspondence matched filter’s FPGA designs the [J] microcomputer to plan the information, 2005.3:117-119
[5] digital communication, John G.Proakis, electronics industry publishing house, in February, 2004
