Abstract introduction take Philips LPC3180 micro controller as core embedded software and hardware platform design; Carry on the detailed analysis to system design’s hardware part and the software part, and aimed at the LPC3180 chip characteristic to discuss its software system construction as well as the system initiation flow emphatically. The experimental result indicated that the LPC3180 embedded system platform union internal hardware floating point calculation unit, has the high performance floating point calculation handling ability, may satisfy the complex embedded application situation the request.
Key word LPC3180 ARM9 software and hardware platform
Embedded application system design including hardware platform and software platform two parts. The former is take inserts declines the controller/microprocessor as the core hardware system; The latter is revolves the embedded operating system construction the software system. Both in the design are inseparable, and needs to carry on the balance between the design to optimize, carries on outside according to the practical application expands and cuts out.
Interior integrated the rich peripheral device resources based on ARM926EJS the essence LPC3180, has provided the very big design space for the embedded system construction. This article unifies the author to develop the LPC3180 embedded platform the practical experience, will introduce that specifically this system realizes, the structure composition and the experimental result.
1 LPC3180 chip characteristic introduction
LPC3180 is a section of ARM9 micro controller which Philips Corporation promotes newly. It uses the 90nm processing technology, internal integrates the ARM9EJS processor essence, has the high estimated performance, the low power loss characteristic, this enabled in still many to use the high performance to the power loss sensitive embedded application situation in the ARM9 micro controller. The LPC3180 essence normal work voltage is 1.2V, may drop to 0.9 under the low power loss pattern V; At the same time, LPC3180 takes model of new 32 micro controllers, its new characteristic also includes:
◆ internal integrated vector floating point (VFP) cooperates the processor. The LPC3180 floating point calculation unit has 3 independent assembly lines, supports the parallel single precision or the double precision floating point adds/reduces, while/dividing and while the accumulation operation, the completely compatible IEEE754 standard, is suitable for the high speed floating point calculation situation.
◆ internal integrates USB the OTG control module, simultaneously supports and the portable USB main equipment or the USB peripheral device is connected, may use in with PDA, reading and printer equipment and so on card direct connected, but does not need the PC machine involvement.
◆ LPC3180 uses multi-layered the AHB bus system, provides the independent main line for each host module, including CPU command line and data bus, 2 set of DMA controller data bus as well as 1 set of USB controller data bus.
LPC3180 internal construction as shown in Figure 1. 
Figure 1 LPC3180 interior construction
LPC3180 other characteristics include: Internal integrates the MLC/SLCNAND controller, SDR/DDR the SDRAM controller, the SD card connection, UART, SPI, the I2C periphery connection module, as well as high speed/millisecond timer, RTC, watch-dog timer, 10 ADC and so on other functional module.
2 hardware platform design
As core hardware platform design frame as shown in Figure 2 take LPC3180.
Figure 2 LPC3180 hardware platform design diagram
(1) memory system
NAND Flash memory. Through LPC3180 internal integration MLC/SLC NAND controller direct external connection multistage or single stage NAND Flash component. This system selects ST NAND256R3A, its 32 MB storage space may satisfy the depositing system vectoring procedure, the embedded operating system essence and filing system’s size request.
SDRAM memory. The system selects 2 piece of 16 MICRON SDRAM, constructs 32 SDRAM memory system parallel. 32 MB the SDRAM space, may satisfy the embedded operating system as well as the upper formation application procedure movement request.
SD card slot. The system through LPC3180 the internal integration’s SD card connection, provides the SD card slot, may use in outside the SD memory stick expanding, takes the exterior storage space.
(2) periphery correspondence connection
UART connection. LPC3180 internal integrated the standard UART module and the high speed UART module, conforms to 550 industrial standards. Outside the system expanded UART1/7, UART2 and UART5, uses in realizing the basic serial communication function; At the same time, UART5 may use when the system initiation exterior procedure downloading.
USB connection. LPC3180 internal integrated USB host, USB device as well as USB the OTG controller, expands USB host through exterior USB receiving and dispatching module Philips ISP1301 outside connection A, USB device connection B as well as USB OTG connection AB.
(3) other periphery module
The system expanded a simple character LCD display module through the I2C connection outside, uses in the application program run result demonstration; Outside at the same time, to simplify the hardware system design, system’s ethernet module realizes through USB host connection A by the software way expands.
3 system essential module design
3.1 NAND Flash memory module
LPC3180 internal integrated MLC/SLC the NAND controller, through the exterior pin may the direct external connection multistage or single stage NAND the Flash component, as shown in Figure 3. What needs to pay attention is MLC and SLC the NAND controller through the pin multiplying, uses the same connection and NAND Flash is connected, and the identical time only permits an opening controller, therefore after system electricity must through dispose the NAND controller which the FLASH_CTRL register choice must use. When leaves unused the condition, may also through write the register to close the NAND controller, reduces the power loss. NAND the Flash memory module is the overall system main static state data storage space, uses in the memory system startup procedure the loading sequence, therefore in the LPC3180 system design is essential.
Figure 3 NAND Flash connection connection diagram
3.2 USB interface module
LPC3180 internal integrates the USB control module, but including the USB physics level, the system does not realize the USB physical level connection through external connection USB receiving and dispatching module ISP1301. Figure 4 is the USB connection connection diagram. The LPC3180 interior disposes the USB controller through AHB from the equipment main line, may work in full speed (12 Mb/s) and the low speed (1.5 Mb/s) under two kind of patterns.
Figure 4 USB connection connection diagram
4 software system design
Software system composition including system vectoring procedure Bootloader, embedded operating system as well as upper formation application procedure. And Bootloader is the movement before operating system’s vectoring procedure, before the primary mission is completes the system initiation, the essential hardware initialization and the operating system load; The operating system is the entire embedded platform kernel program, the major function is manages and assigns the first floor hardware source highly effective, and provides the system call connection which for the upper formation application procedure has nothing to do with the hardware detail.
The software system design must unify closely with the hardware platform. LPC3180 uses NAND Flash to take overall system’s procedure to save the region, when system initiation through the piece on the ROM bootstrap procedure, loads and carries out the exterior vectoring procedure to realize overall system’s start step from NAND Flash. Therefore, the entire software system has adopted the design structure which shown in Figure 5.
Figure 5 software system structure diagram
(1) system vectoring procedure Bootloader
Because the startup procedure first starts from the internal bootstrap procedure, therefore the system adopts the second-level Bootloader design, including first level of Sibl and second level of U 瞓 oot.
And Sibl is the first vectoring procedure which bootstrap loads and carries out, is restricted which in the procedure size bootstrap loads, therefore designed on has achieved the miniaturization and the function as far as possible is single-minded. It besides completes the most basic hardware initialization, the major function is realizes other procedures (including U 瞓 oot) from the NAND Flash load, before under completing the first-level Bootloader movement memory address space distribution.
Second level of Bootloader uses function formidable sourceforge to open source software U 瞓 oot. Before the U 瞓 oot major function is completes the embedded operating system to start the first floor hardware initialization, and is the Linux essence provides the start parameter, final pilot operation system Linux essence start. Moreover, to realize the procedure mirror image document programming to read in NAND Flash, U 瞓 oot to insert a NAND subsystem, realized through the U 瞓 oot user command line to NAND Flash reads/writes the operation, might read in the procedure mirror image the address space which NAND Flash assigned.
(2) embedded operating system
LPC3180 internal integrated the ARM926EJS processor essence, brings memory management unit MMU, supports the most mainstream embedded operating system. The system through the compilation board level support code, transplanted Linux2.6.10 to take the platform operating system, used the stable Linux2.6 essence to realize functions and so on task scheduling, process management, memory management, simultaneously, in view of Linux configurable, carried on cutting out and the hardware to the essence actuates the code to increase, the system has realized one small, but the function formidable kernel program, adapted the embedded system memory resources relatively scarce condition.
5 system initiation flow analysis
Is composed the analysis by the above software architecture to be possible to know, the overall system start flow divides into 3 steps:
① On after system electricity, first bootstrap program execution which ROM solidifies from the piece. bootstrap uses in completing the exterior vectoring procedure to download and to plunge into the execution. the bootstrap movement process first reads input pin GPIO_01. If GPIO_01 set to high, from NAND Flash downloading pre-computed course system initiation; If set to lowly, then examines the USB connection and the UART5 connection in turn, through the exterior connection downloading vectoring procedure. The system through establishes GPIO_IO to jump the line to control the bootstrap startup procedure, this example set at to high GPIO_01, from NAND Flash downloading procedure.
② The system initiation’s second stage is movement bootstrap downloading vectoring procedure Sibl. After Sibl completes the system essential initialization, from NAND the Flash load mirror image procedure to the SDRAM space which assigns. The mirror image procedure increased 64 byte head information in the reference, uses in the Sibl recognition and the load, the message data structure is as follows:
struct image_header {
uint32_tih_magic; /* mirror image information synchronization character, Sibl through this character recognizer */
uint32_tih_hcrc; /* mirror image information CRC verification code */
uint32_tih_time; /* memory mirror image foundation time */
uint32_tih_size; /* mirror image data size */
uint32_tih_load; /* mirror image load address */
uint32_tih_ep; /* mirror image entry point address */
uint32_tih_dcrc; /* mirror image data CRC verification code */
uint8_tih_os; /* operating system information */
uint8_tih_arch; /*CPU architecture type */
uint8_tih_type; /* mirror image type */
uint8_tih_comp; /* compression type */
uint8_tih_name[32]; /* mirror image name */
}
Sibl start address starts from NAND the Flash to search. If reads mirror image synchronization character ih_magic, then the recognition mirror image procedure, and according to offset address read procedure size ih_size and load address ih_load, to assigns the program load SDRAM space; After the load completes, carries on the CRC examination according to CRC verification code ih_dcrc to the SDRAM data; Finally according to mirror image type ih_type judgment mirror image whether can carry out, if may carry out, then plunges into mirror image entry point address ih_ep, otherwise Sibl continues to search NAND the Flash mirror image procedure.
The mirror image procedure uses tool mkimage which U-boot provides to add raises interest rates the information, the forms of field orders is as follows:
mkimage-A arch-O os-T type-C comp-a addr-e ep-n name-d data_file image
Figure 6 system initiation process memory space distribution map
③ After completing the Sibl load, memory spatial distribution as shown in Figure 6, the system enters the start flow third stage U-boot. Before U-boot completes the Linux essence mirror image the solution compression and the operating system starts the initialization, plunges into the essence entry point address finally, completes to the Linux guidance.
6 system performance analyses
The system construction provided a complete LPC3180 embedded software and hardware platform, below has carried on the test and the analysis to the LPC3180 floating point calculation ability. The test method uses a floating point calculation crowded algorithm, translates separately with the ADS compiler enables hardware VFP and the soft floating point calculation two edition test orders, and compares the running time under the different CPU clock rate, result like table 1 arranges in order.
The analysis empirical datum, may draw the conclusion: VFP cooperates the processor under the same clock rate, enhanced 5 time of about floating point calculation performance. Therefore, the LPC3180 platform unifies VFP to cooperate the processor, can realize the complex floating point calculation crowded algorithm. Integrates the hardware floating point calculation unit in the micro controller, this causes the micro controller’s data-handling capacity to enhance greatly, can be competent the most digital signal processing application.
Table 1 floating point calculation result
Conclusion
This article introduced with realizes take the LPC3180 micro controller as the core embedded software and hardware platform’s design, and tested, has confirmed the LPC3180 floating point calculation performance. This platform has regarding the LPC3180 application development profits from the significance. At present LPC3180 in domains and so on medical instrument, industrial control, POS machine, digital signal processing has the widespread application.
Reference
[1] LPC3180 User Manual. http://standardics.philips.com.
[2] ISP1301 User Manual. http://semiconductors.philips.com.
