Abstract: Based on the embedded system need to develop, proposes TMS320VC5402 DSP and at89C51 monolithic integrated circuit correspondence three kind of design proposal. Realizes TMS320VC5402 and AT89C51 SCI and the SPI serial communication separately using TMS320VC5402 multichannel cushion serial port MCBSP, as well as one 8 realizes TMS320VC5402 and at89C5l parallel correspondence through TMS320VC5402 8 enhancement host interface HPI. Carries on the detailed elaboration on the hardware interface electric circuit and the software programming.
Key word: Monolithic integrated circuit DSP MCBSP HPI
Form a pair the CPU processor platform DSP and the monolithic organization, may use DSP fully to the large capacity data and complex algorithm handling ability, as well as monolithic integrated circuit connection control. But between DSP and the monolithic integrated circuit the fast correct correspondence constructs the double CPU processor’s key question. Below designs serial SCI, SPI and the parallel HPI three connection modes separately on this question.
1 serial communication design with realizes< ?XML:NAMESPACE PREFIX = O />
1 1 SCI serial communication design
1.1.1 multichannel cushion serial port McBSP principle
TMS320VC5402 (i.e. VC5402) provided 2 supports to be high speed, merit and so on full-duplex, belt cushion, many kinds of data formats multichannel cushion serial port McBSP. MCESP divides into the data path and the control path.①The data path completes the data responsibly receiving and dispatching. CPU or DMAC can the data transmission register DXR write data, in the DXR data output the DX pin through transmission shift register XSR. The DR pin receive data to receive shift register RSR, duplicates receive cushion register RBR again, finally duplicates data receive register DRR. These two data multistage cushion ways cause outside the data removal and the piece the data communication can also carry on.②The control path is responsible for the internal clock production, the frame synchronizing signal production, the signal control and the multichannel choice. Moreover. Also has to the CPU transmission signal of stop and to the DMAC transmission synchronization event’s function. The MCBSP clock and the frame synchronizing signal through CLKR, CLKX, FXR, the FSX pin carry on the control, the receiver and the transmitter may choose the external clock and the frame synchronizing signal independently mutually, may also choose by the internal sampling rate generator produces the clock and the frame synchronizing signal. Frame synchronization pulse effective expression transmission start.
1.1.2 SCI serial interface design
Establishes VC5402 the McRSP output clock and the frame synchronizing signal by the internal sampling rate generator production, internal data clock CLKG and frame synchronizing signal FSG actuation transmission clock CLKX and the frame synchronization FSX(CLKXM=l, FSXM=l, FSGM=1), the input clock also by the internal sampling rate generator production, the internal data clock CLKG actuation receive clock CLKR(CLKRM=1), simultaneously actuates the sampling rate generator by the CPU clock (CLKSM=1). Considered AT89C51 (i.e. C51) in the serial port transmission data frame lth is the outset position, therefore may use this actuation input frame synchronizing signal FSR, simultaneously must set neglects the frame synchronizing signal symbol is 1. And FSG frame synchronization pulse width = (FWID 1) · CLKG; FSG frame synchronization repetition interval = (FPER 1) · CLKG; Sampling rate generator frequency division coefficient (sampling rate = baudrate) =FIN/(CLKGDV 1).
SCI serial port connection like chart l shows.
1.1.3 baudrate inconsistent processing
The VC5402 initialization (take Figure 1 as example):
STM#SRGRl, SPSAl
STM#ooFEH, SPSDl; The FSG frame synchronization pulse width position is 1 CLKG
; The baudrate is 100 MHz/(0X(OFF) =392 156 b/s
STM#SRGR2, SPSAl
STM#3D00H, SPSDl; The internal sampling rate generator clock actuates by CPU
C51 initialization:
MOV TMOD,#20H
MOVTLl,#FFH
MOVTHl,#FFH; C51 baudrate = (2SMOD/32) * (fosc/12) [1/(2561 starting values)]24 509 b/s
MOV SCON,#50H; Sets at serial port way l, each 10 bit data. Permission receive
MOV PCON,#80H; Establishes SMOD=1
VC5402 baudrate /C51 baudrate = (392 156/24 509) =16.000 49
VC5402 transmits 16 bit data every time, the C51 sampling 1 bit data. Opens a space in the VC5402 memory to 8 bit data which each time transmits to carry on the expansion, 1 expands is 16, 0 are 0000H, l is FFFFH, altogether expands is 128. Fills in Canadian 16 outset position 0000H in the data forehead, the data rear part fills in adds stop position FFFFH. Establishes XWDLEN=000 in VC5402 in transmission control register XCR (1 character including 8), is going to transmit 8 bit data seal 1 10 characters the data. This also conforms to the C51 serial port 1 way next 1 10 data format. C51 take 1/16 VC5402 sampling speed receive data, the 0000H sampling as the 0, FFFFH sampling is 1, from this may 200 which receives restore is 8 bit data, stops the position entering RB8.
C51 transmits 1 bit data, VC5402 wants the sampling is 16 bit data every time. C51yi transmission’s 10 bit data’s outset positions trigger VC5402 the receive frame synchronization. As a result of VC5402 take 16 time of C51 sampling speed receive data, 1 sampling as 16, 0 sampling are the 0000H,1 sampling are 10 first 9 which a FFFFH. sampling transmits, 9 seal 144, namely the receive 1 data completes. VC5402 will receive 144 bit data in opening memory space depositing, get rid of first 16, in is left over in 128 divides into 8 groups, each group of 16. Compared with 8, if has above 4 is 1, then these 16 are 1, otherwise is 0. From this will receive 144 restore is 8 bit data.
For does not let CPU frequently by the data receive and the transmission interruption, uses the control data receive and the transmission jointly DMA and MCBSP. RRDY direct drive MCBSP to DMAC receive data event (REVENT event), XRDY direct drive MCBSP to DMAC transmission data event (XEVENT event).
SCI communication protocol as shown in Figure 2
1. 2 SPI serial communication design
Sets at C51 for the main engine, VC5402 is from machine. The McBSP clock stops the pattern (CLKSTP=1X) compatible SPI pattern, the receiving unit and the transmission partial interior synchronization. McBSP may take SPI from machine or the main engine. Transmission clock BCLKX takes SPI the agreement the shifting clock SCK use, transmission frame synchronizing signal BFSX takes from machine enables the signal nSS use, receives clock BCLKR and receive frame synchronizing signal BFSR does not use. They in interior separately with BCLKX and BFSX direct connection. BDX as MISO, but BDR takes MOSI, the transmission and the receive have the same word length.
In C51 and mouth P1.1 and P1.2 lose the person outlet and the VC5402 connection as expansion serial SPI, P1.0 take the serial clock outlet, P1.3 take frame synchronizing signal outlet _.
SPI serial port connection as shown in Figure 3.
The VC5402 initialization routine (take Figure 3 as example):
STM#SPCRll, SPSAl; Establishes the clock to stop the position entering MCBSP the SPI pattern
STM#0X1000, SPSDl; The clock starts in the rise along (does not have detention)
STM#SPCRl2, SPSAl
STM#0X0040, SPSDl; XINT (i.e. suffix) actuates by XRDY
STM#PCRl, SPSAl
STM#0X000C, SPSDl; To transmits with the receive clock, the synchronized frame carries on the establishment
STM#RCRll.SPSAl
STM#0X0000, SPSDl; Receive data l 1 character .1 character 8
STM#XCRll, SPSAl
STM#0X0000, SPSDl; ; Transmission data 1 1 character .1 character 8;
P1.0 transmits to the VC5402 shifting clock is guarantees the DSP correct sampling receive and the transmission data clock. It must guarantee and the C51 sampling receive and the transmission data clock is consistent. Can cause main from machine the synchronization.
2 parallel correspondence designs with realize
2.1 VC5402 HPI connection principles
HPI one 8 are 8 (HD0~HD7) connection DSP and the main engine equipment or the main processor’s parallel interface. DSP and the main engine through the DSP internal RAM exchange data, entire internal RAM may take HPI 8 memories. The HPIA address register can only visit directly by the main engine, depositing current addressing memory’s address; The HPID data latch can only visit directly by the main engine, depositing current needs to read in or the read-out data; The HPIC control register may visits together by the main engine and VC5402. HPI hardware interrupt logic may complete main from equipment’s handshake, the main engine through sets in the HPIC special localization to have the DSP interrupt, similarly DSP has the interrupt through the nHINT pin to the main engine. The HRDY pin uses in the automatic control main engine visiting HPI the speed, causes the slow exterior main engine and DSP can match well. HRDY enables by HCS, namely, when HCS is high HRDY continuously for high, but when EMUl/nOFF is low, HDRY outputs high-resistance.
HPI connection as shown in Figure 4.
2.2 parallel interface designs
Sets at C51 for the main engine, VC5402 sets for from machine. The C51 PO mouth and the HPI 8 bit data line HD0~HD7 connected achievement data-transmission channel, P1.0~P1.3 establishes as the output control HPI mouth operation. And P1.0 connects HR/W as the read-write control gating signal; P1.1 connection byte identification signal HBIL, the control read-write data belongs to the 16 bit word 1st 2nd byte; P1.2 and P1.3 connect HCNTL0 and HCNTLl separately, realizes visit to HPIC, HPIA and HPID register’s; nRD and nWR connect nHDSl and nHDS2 lock as the data gating signal save effective HCNTLO/1, HBIL and the HR/W signal. nINTl as the input, is connected with HPI mouth main engine signal of stop nHINT. nHCS has earthed, but the nHAS mouth and the ALE mouth connect, after HCNTL0/I, HBIL and HR/W signal effective, establishes nHDSl is the low level, then has realized the read-write data selection, thus completes C51 to VC5402 the HPI mouth read-write operation. When data exchange process, C51 to HPI transmission data, through sets at VC5402 HPI in the control register HPIC DSPINT position is l interrupts VC5402. C51 receive from when HPI data through inquiry way, when VC5402 DSP preparation transmission data, set at the nHINT signal lowly to; C51 inquires when nlNTl is low, the transfer receive data subroutine realizes the data receive.
C51 and VC5402 parallel connection as shown in Figure 5.
Main engine receive and transmission initialization routine (take Figure 5 connection as example):
RTITEADDRESS: ; Reads in the VC5402 memory address message
CLR P1.2
Note:①The HBlL foot instructs the current byte in the transmission process for the l 2nd byte.
②In order to facilitate DSP from lifts the guidance loading sequence. Often uses the nHlNT foot is direct and INT2
The foot is connected.
Figure 5 AT89C51 and V05402 parallel connection
SETB P1.3 ; The main engine may the read-write HPlA address register
CLR P1.0 ; The main engine request writes selects HPI one 8
MOV P0, A ; Reads in 8 bit addresses
CALL DELAY; The waiting address reads in completes
READDATA: ; Reads out the VC5402 memory data message
SETB P1.2
CLR P1.3 ; The main engine may the read-write HPID data register
SET P1.0 ; The main engine request reads selects HPI one 8
MOVA, P0 ; Reads out 8 bit data
CALL DELAY; Waited for that the data read-out completes
WRITEDATA: ; Reads in the VC5402 memory data message
SETB Pl.2
CLR P1.3 ; The main engine may the read-write HPID data register
CLR P1.0 ; The main engine request writes selects HPI one 8
MOV P0, A ; Reads in 8 bit data
CALL DELAY; The waiting data reads in completes
No matter is the serial connection or parallel connects, must consider VC5402 is uses 3.3 V power supplies, C51 uses 5 V power supplies. Between both has the signal level the difference, but cannot direct connected, should interlock the connection isolation component.
Conclusion
In the SCI serial communication debugging, discovered that because the DSP movement frequency about 100 MHz, causes internal data clock CLKG to be excessively quickly, cannot maintain consistent with the C51 serial port sampling frequency, needs the software to process, like this can extra consume the DSP resources. Therefore may consider that will transmit clock CLKX and receive clock CLKR meets the external clock source (slowly in the DSP clock), guarantees with the C51 serial port sampling frequency consistency. Moreover in the parallel correspondence’s debugging, may know that does not have hardware and the software overhead completely through the HPI-8 mouth parallel correspondence, is coordinated by DSP own hardware conflicts, therefore HPI-8 mouth use in and monolithic integrated circuit component good host from double CPU processor platform.
