Introduction
Along with computer technology’s development and the widespread application, are particularly getting more and more widespread in the industrial control domain’s application, computer correspondence important especially obviously. Although the serial communication causes between equipment’s segment is the reduction greatly, but brings the string along with it/and transforms and questions and so on position counting, this makes the serial communication technology to be more complex than the parallel communication. The string/and transforms the available software to realize, also the available hardware realizes. Realizes the serial transmission with the software mostly to use the end around shift instruction (or low position to top digit) transmits in turn a byte from the top digit to the low position, although this method simple, but the speed is slow, moreover takes CPU massively the time, affects system’s performance. More convenient realizes the method is with the hardware, at present the microprocessor serial interface commonly used LSI chip is UART (general asynchronous transceiver), USART (general synchronized asynchronous transceiver) and ACIA (asynchronous communication interface adapter) and so on. Which one kind of chip no matter is, their one kind of basic function is realizes the string/and transforms. Was precisely these serial interface chip makes up the serial communication to be more complex this flaw. This article applies EDA (electronic design automation) the technology, (the scene programmable gate array) /CPLD (complex programmable logical component) designs based on FPGA with realizes UART.
1 system design
Entire design including two parts: Based on FPGA UART design and based on VB6.0 superior machine programming. The UART design uses modular the design concept, may divide into 3 modules: FPGA data transmission module, FPGA baudrate generator control module and data receive module. The superior machine procedure uses VB 6.0 Mscomm to control, may divide into the picture design and the functional design two parts. The serial port uses the standard the RS-232 agreement, the main parameter choice is: Baudrate 9 600 bit/s,8 position significant digit, non-parity check position, 1 stop position.
2 UART structures and frame form
UART mainly includes the receiver and the transmitter. Receives from asynchronous receive input signal SIN to the asynchronous signal completes the serial/parallel transformation through the receiver, forms the asynchronous data frame; Transmitter 8 bit data which sends out CPU carry on the parallel/serial transformation, transmits from SOUT. The function including the microprocessor connection, TBR (transmits buffer), TSR (transmission shift register), the frame to produce, and transfers the string, RBR (to receive buffer), RSR (receive shift register), the frame to produce, the string to transfer and. UART structure as shown in Figure 1.
The UART frame form including the line idle condition (idle, high level), the outset position (start bit, low level), 5 ~8 bit data positions (da-ta bits), the verification position (parity bit, may choose) and the stop position (stop bit, figure may be 1, 1.5, 2). This kind of form is realizes the character synchronization by the outset position and the stop position. The UART interior has the disposition register generally, may the layout data figure (5 ~8), whether to have the verification position and the verification type, the stop position figure (1,1.5,2) and so on establishments.
3 UART designs with realize
UART is the widespread use serial data transmission agreement. The UART permission carries on full-duplex’s correspondence on the serial link. The serial peripheral device uses the RS-232-C asynchronous serial interface, generally uses the specific IC is UART realizes. Like chips and so on 8250, 8251, NS16450 are the common UART components, this kind of chip was quite already complex, some include many auxiliary modules (for example FIFO), sometimes does not need to use complete UART the function and these auxiliary functions, or has used FPGA/CPLD, then may need the UART function integrates in FPGA. Uses VHDL the UART core function integration, thus causes the entire design to be more compact, to be stable and is reliable.
Below designs UART separately 3 modules (transmitter, receiver and baudrate producer), and gives its simulation result.
3.1 transmitter designs
UART serial transmitter module diagram as shown in Figure 2. DIN is 8 bit data, other are 1.
Diagram may see from Figure 2, in the serial transmitter contains has 8 THR (transmission maintains register) and TSR (transmission shifting checks). When replacement, pin TRE is the high level. After the data writes down TSR, pin TRE becomes the low level. End of transmission, TRE became the high level. When detects inputs WRN becomes the low level, automatically enables the serial data sending process. First transmits 1 outset position (logic level 0), simultaneously in the THR data parallel writes down in automatically TSR. Then, the fixed-length data position emigrates from TSR, then verifies the position. Finally, has the stop position (logic level 1), symbolizes a conclusion. Serial data frame by internal clock frequency 1/16 transmission. If in THR the content is not spatial, when after a serial data frame transmission had ended, is following closely the transmission next data frame. This kind of automatic flow causes the data frame by the way transmission back to back, enhanced the data transmission band width. When does not have the data transmission, the SDO pin maintains the high level.
The transmitter every other 16 clock cycles output 1, follow 1 outset position, 8 bit data positions (hypothesis data position are in turn 8), 1 bit check position (may choose), 1 stop position. The introduction transmission character length and transmission order counter no_bits_sent, realizes the part VHDL procedure is as follows:
Transmitter function simulation result as shown in Figure 3. Parallel input DIN the sexadecimal number 56, WRN input by 1 becomes 0, the shoulder moves the calling order, the counter starts to count, serial output SDO is 0010101101, end of transmission, TRE became the high level. The outset position 0,8 bit data positions, 1 stop position, has proven the transmission module accuracy.
3.2 receiver designs
UART serial receiver module diagram as shown in Figure 4. DOUT is 8 bit data, other are 1. The receiver contains 8 RBR and RSR. The RBR condition may through the pin DATA_READY rice expression. When in the RBR data is effective, DATA_READY becomes the high level, to CPU indicated that may take the same data.
So long as this design strives for realism presently the simple receiving and dispatching function, therefore has not designed the error detection procedure, the procedure after detecting the outset position, counts 16 clock cycles, then starts to receive the data, carry input RSR, final output data DOUT. Must output a data accepted flag marker data to receive. Realizes the part VHDL procedure is as follows:
Acceptor function simulation result chart slightly. Serial input RXD is 0010101101, each accounts for 16 clock cycles, once examines inputs RXD is 0, the counter started to count, starts to receive the data, the receive finishes, the flag bit became the high level. The simulation result has proven the receive module accuracy.
3.3 baudrate generator design
The UART receive and the transmission defer to the same baudrate to carry on receiving and dispatching. The baudrate generator produces the clock rate is not the baudrate clock rate, but is baudrate clock rate 16 times, the goal is for when the receive carries on precisely the sampling, proposes the asynchronous serial data. According to the crystal oscillator clock which and the request baudrate assigns figures out the baudrate frequency division number. Realizes the part VHDL procedure is as follows:
Baudrate function simulation result chart slightly. The input frequency is 20 MHz, the profile cycle is 50 ns,20 MHz/(9 600 bit/s×16 bit) =130, may know output wave shape by the simulation result a half cycle is 65 time of input clock cycle, thus has proven the baudrate producer module accuracy.
4 superior machine programming
This article uses VB 6.0 to carry on the superior machine procedure the design, realizes PC and the FPGA serial communication. Below is 1 superior machine receiving and dispatching test signal procedure design process, may carry on the serial communication through this procedure with FPGA. The baudrate default value is “9600, N,8,1″, its Italy for the communication port which uses is by 9 600 bit/s speed transmissions, does not make the character check, data each time is 8, but stops the position is 1. The baudrate (unit is bit/s) may be 110, 300, 600, 1200, 2400, 9 600, 14 400, 19 200, 28 800. The verification position is: E occasionally verifies, N does not have the verification, the O wonderful verification, the S blank. The correct data position value includes: 4th, 5, 6, 7, 8 (default value). The correct stop position value includes: 1 (default value), 1.5, 2.
After UART program compiling, simulation, downloads to the FPGA EPlK30TC144-3 chip. Introduces 20 MHz the crystal oscillator frequencies; The transmission enables the end and the replacement end meets a switch separately; The condition output symbolized that TRE and DATA-READTY meet a diode separately, the instruction condition; The establishment baudrate is “9 800, N,8,1″. The serial data frame’s form is: The outset position 0,8 bit data positions, do not have the verification position, 1 stop position. The UART serial transmission, receives the port separately with computer’s RS-232 serial receive, the transmission port connection, in order to carries on the serial communication with PC machine; Parallel input DIN turns on parallel output DOUT; After Lian Haoxian, execution transmission test order.
5 concluding remark
In realizes FPGA and in the PC serial communication, downloads the procedure to the chip in confirms the design the accuracy, at present did not have a better tool to be possible when downloads the well off to the FPGA working condition and the data carries on the analysis. Through the serial communication, may send the control command to FPGA to let its execution corresponding operation, simultaneously the data which needs through the serial port sends on PC to carry on the corresponding data processing and the analysis, judges FPGA by this whether to press the design requirements work. This article as the key point discussed FP-GA and the superior machine serial communication take UART realizes the method. Used higher order language VB to realize the superior machine and the FPGA correspondence.
