Introduction
Along with industrial technology’s unceasing development, the request which controls to the monolithic integrated circuit is also getting higher and higher, needs the monolithic integrated circuit to have the higher reaction rate and stronger data-handling capacity, each kind of high performance’s new monolithic integrated circuit obtained the swift and violent development and the application. On the monolithic integrated circuit is mainly the high speed digital signal, the weak signal is very easy to receive the outside the electromagnetic interference, simultaneously, the monolithic integrated circuit system will also give rise to problems and so on power failure, endless loop. In industrial control situation, once controls has the mistake, will cause the inestimable losses. Therefore, how enhances the control the reliability is a since long important question. This article introduced applies 32 high performance monolithic integrated circuit MC68HC376 one kind of actual development program, simultaneously discussed with emphasis enhanced the system reliable design and realizes the method.
MC68HC376 is one kind of new 32 high performance monolithic integrated circuit which Motorola Corporation promotes, has the greatly strengthened data processing, the logic operation and information storage ability, and supports BDM (Background Debug Mode) the pattern. Through the simple special cable connection, may carry on the simulation development and the fever directly to the micro controller system records the procedure. In addition, because the MC68HC376 interior integration rate is high, the exterior expansion works few, therefore itself has the strong antijamming ability; Meanwhile through the external hardware electric circuit as well as software’s antijamming design, the control system may realize the high reliability.
1 control system’s basic structure design
The MC68HC376 integration rate is high, its major function module including 32 CPU; System integration module (SIM); 4K spare RAM; 8K internal ROM; 10 formation’s-like modulus switch (QADC); Formation type serial communication module (QSM); May construct the clock module (CTM4); Time processing unit (TPU);
3.5K static TPURAM; CAN control module (TOUCAN). Its key property is as follows:
(1) 24 bit address main line, 16 bit data bus structure, supports 32 bit data operations.
(2) 2 8 double function I/O,1 7 double function I/O,16~44 simulation quantity input channel.
(3) has the system protection logic, simultaneously may carry on the clock surveillance and the main line surveillance.
(4) speed is quick, the system clock may reach 20.97MHz under the 4.194MHz crystal oscillator.
(5) power loss is low, has the low power dormancy function.
(6) support higher order language and background debugging.
The system expands the basic structure MC68HC376 interior integration rate is high, thus its needs the periphery expansion work are few. The basic structure including exterior Flash ROM, RAM, the simulation quantity input channel, the digital quantity input channel, the keyboard, the liquid crystal display, RS-232 level switch MAX232 and CAN controller CAN250 and so on, its structure diagram as shown in Figure 1. This article key discussion system’s reliability design.
2 system’s reliability designs
2.1 microprocessor hardware monitoring circuit
This article uses the monitor MAX705 chip to constitute the exterior monitoring circuit, electric circuit exterior wiring as shown in Figure 2. This electric circuit has the watch-dog timer, automatic and the hand reset function, as well as voltage threshold monitor function.
Because on system electricity, power failure as well as time power line voltage insufficiency, CPU and the main line logic condition is indefinite, therefore should maintain the micro controller at the replacement condition, avoids controlling the mistake. Regarding MAX705, the replacement threshold voltage is 4.65V, therefore, when Vcc is lower than 4.65V, the system maintains at the reset state. At the same time, is connected Vcc and the PFI pin, when Vcc is lower than 1.25V, warns the signal by the PFO pin output, if the long time is at the power source to warn the condition, then possibly presents the power failure, should perform to process.
When system normal operation, channel is smaller than by MC68HC376 CTM4 the module CTD4 the 1.6s gap fixed time provides the pulse to the MAX705 WDI pin; When the system cannot the normal operation cause MAX705 the WDI pin loses the pulse, the watch-dog fixed time overflows causes /WDO is low, because /WDO and hand reset pin /MR is connected, therefore the /RESET foot sends out the low effective reset signal to MC68HC376, causes the system recovery to the reset state.
2.2 exterior filter circuits
Because the system uses exterior reference frequency source, to raise the system frequency the stability and the reliability, therefore needs to turn on the filter circuit on the MC68HC376 XFC foot. This electric circuit should reduce the XFC foot’s revelation electric current as far as possible, enhances clock’s stability and the internal phase-locked loop performance. Shown in Figure 3 for the high stable filter circuit.
2.3 output driving circuit reliability design
The control device through carries on the monitor and the analysis after the system condition, to control and the adjustment movement unit provides the control signal. If the output signal receives the disturbance or sends out the wrong control signal as a result of the plant failure, then because of will have the wrong regulating control movement to cause the system to receive the harm. Therefore, should perform the corresponding block system control and the antijamming design regarding the output driving circuit, enhances the control the reliability.
; (1) block system control circuit
Here uses may trigger pair of/monostable multivibrator 74LS123 to constitute the output exclusive circuit again, electric circuit wiring as shown in Figure 4. Channel is connected the 74LS123 A foot and MC68HC376 CTM4 the module CTD4, because CTD4 fixed time provides the pulse in the normal condition, enables the oscillating circuit to have the turn over, this time, /Q maintains is 1; If the plant failure, causes CTD4 to lose the pulse, then the oscillating circuit causes /Q to turn over becomes 0, therefore the block system signal becomes 0 pair of output control signal block system.
At the same time, and gate 4081 another foot meets to MC68HC376 TPU the module TCH15 foot, controls directly by MC68HC376. In normal operation, when needs the output control signal, sets at TCH15 is 1; When does not need the output control signal, sets at TCH15 is 0, then causes the block system signal is 0, the block system output unit, has like this prevented, because disturbs the misoperation which or other reasons create.
(2) control signal output unit antijamming design
When block system signal clear, the output control signal possible as a result to disturb presents the deviation, therefore should design the corresponding output circuit form to reduce the perturbation the influence. Output circuit’s form as shown in Figure 5 (here only to draw a group output signal).
Uses when the single track controls, once receives the disturbance to cause the control signal the level to change, thus creates moves by mistake. Here uses “0,1″ the control mode, approaches the pilot wire with two, meets directly to and gate 4081, another 4069 meets after the complementer to 4081, namely, when two pilot wires are “0,1″ outputs the effective level signal 1. Thus, when has the high perturbation either the low perturbation causes the pilot wire simultaneously becomes 1 or 0, outputs the invalid level signal 0. In this system, pin and the block system signal controls the opening signal together by CTM4 the module CPWM7; Opening signal and MC68HC376 control signal together control action output signal. This fully enhanced the output control reliability. The attention, monolithic integrated circuit’s I/O control signal should use on pulls the resistance.
2.4 power failure alarm circuit
When system’s some first-level work power source power failure, the control device will not be able to operate normally, or the control signal cannot obtain the correct execution. By now should send out the alarm, power failure alarm circuit as shown in Figure 6. Separates MOC8050 various ranks’ work power source through the pass to serially connect, once has the power failure situation, the power failure warning’s place level by becomes high lowly, start alarm device. Software reliability design
2.5 software watch-dogs
In the MC68HC376 SIM module, some software watch-dog, in the monitor routine, may open the software watch-dog, coordinates to enhance system’s reliability. This software watch-dog protects in control register (SYPCR) by the MC68HC376 system the SWE position control opening. When the SWE position is 1, the watch-dog starts, starts to time. When equipment normal work, the procedure should before the software watch-dog overflow reads in 55H and AAH successively to software service register (SWSR), when after reading in completes, the software watch-dog will eliminate the current time value, makes a fresh start to time.
If time value overflow, will then cause MC68HC376 the /RESET pin to be effective, system reset. Thus, may when the procedure endless loop or causes the procedure ricochet as a result of other reasons replies the reset state automatically.
Watch-dog’s overflow time by system frequency as well as SYPCR register’s watch-dog frequency division position (SWP) and watch-dog fixed time area (SWT[1:0]) decision, as shown in Table 1. When choice watch-dog overflow time should pay attention to the size to be moderate, if the value is oversized, then the procedure long time will possibly be at the endless loop or the ricochet condition, will thus cause the control mistake or the expiration; If the value is too small, will then increase the procedure burden, will cut the installment operating efficiency.
2.6 procedure regionalisms and operation rank control
CPU32 may carry on two kind of first ranks the operations: Monitoring rank and user rank. In monitors under the rank, CPU may carries on the operation to all internal integrated resources and all instructions, but under the user rank, it can be restricted visit to some registers and instruction. Will use this kind of first rank in the procedure to cause the internal resources and some system instruction effectively obtains has the control visit, will thus enhance the systems operation the reliability. In CPU32 condition register SR S decides CPU the work rank, when S=1 CPU is in the monitoring rank; When S=0 CPU is in the user rank.
; In ordinary circumstances, monolithic integrated circuit’s procedure area and data area in identical physical address space. Regarding MC68HC376, may expand and divide the exterior physical space through functional code FC[2:0], realizes the exterior decoding to FC[2:0], may cause the monitoring level procedure, the monitoring level data, the user level procedure, the user level data to use respectively the independent address space separately. Regarding MC68HC376 interior’s each module, may through its corresponding structure register’s in SUPV position determine this part of general registers locate address space, when SUPV=1, will be related the register lays aside in the monitoring level data address space, CPU when monitors the rank only then may visit to its and the operation; When SUPV=0, will be related the register lays aside in the data level data address space, CPU may carry on and the operation willfully visit to it. Thus, entire procedure constitutive, according to the rank control visit, strengthened the movement reliability.
2.7 main line monitoring devices
MC68HC376 carries on when the internal main line operates, the data selection reply pin (/DSACK) and the automatic vector pin (/AVEC) should have the corresponding answering signal. In the SIM module’s main line monitoring device can carries on the surveillance to /DSACK and the /AVEC signal, when the response time surpasses fixed time the value to cause the main line wrong (/BERR) the pin to be effective. The procedure deals with /BERR the condition to carry on the surveillance, with the aim of making corresponding processing wrongly promptly to the main line.
The main line monitoring device’s value fixed time protects in control register (SYPCR) by the system the main line surveillance time area (BMT[1:0]) decision. When BMT[1:0]=00, fixed time the value is 64 system clocks; When BMT[1:0]=01, fixed time the value is 32 system clocks; When BMT[1:0]=10, fixed time the value is 16 system clocks; When BMT[1:0]=11, fixed time the value is 8 system clocks. The programmer should act according to the actual operational aspect to carry on the choice.
Other other enhance the reliable measure also to include the disposition decoupling electric capacity; The system clock electric circuit uses the independent power supply VDDSYN power supply, reduces to the MCU disturbance, when MCU power cut the system clock still might maintain the movement. When wiring, the clock circuit establishes in the circuit wafer central committee; Standby RAM uses two power source VDD and the VSTBY power supply, when normal operation when the VDD power supply, has the power failure, causes its automatic cut over VSTBY power supply. At the same time, in the software, deposits the storehouse and some important data in Standby RAM is advantageous to the important operational factor preservation.
3 conclusions
This plan uses the high performance, the integration rate to be high, reliable strong 32 new micro controller MC68HC376 is a core, simultaneously in aspects and so on hardware, software as well as system board wiring uses many kinds of enhances the system reliable design measure. Installs RSA800 using this plan’s digital low frequency low-pressure control, already through Ministry of Power Industry power equipment and measuring appliance performance test test center product modelling test.
Reference
1 MC68336/376 user’s manual. Motorola.Inc.1996
2 CPU32 reference manual. Motorola.Inc.1996
3 CTM configurable timer module reference manual. Motorola.Inc.1996
4 QADC queued analog-to-digital converter reference manual. Motorola.Inc.1996
5 SIM system integration module reference manual. Motorola.Inc.1996
6 QSM queued serial module reference manual. Motorola.Inc.1996
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