If alphanumeric display terminal for digital micro mirror DMD (Digital MicromirrorDevice) monitor. This monitor the computer each picture element image signal processes after the digital light DLP (Digital Light Processing), stores the SDRAM bidirectional buffer storage, when an image receive finished, the internal data processing electric circuit simultaneously stimulated various picture elements point correspondence the micro mirror movement, completed an image the demonstration. The DMD monitor peak value digit slaving voltage does not surpass 33.5V, the electromagnetic radiation is very low, and each micro lens also actuate, forms the radiation signal which outward disturbs mutually, the decoding difficulty is enormous, thus causes it to become non-information divulging the monitor. This time, the video frequency electric cable’s radiation occupies the dominant position in the entire video frequency circuit’s radiation. If in the video signal transmits the monitor before the video frequency electric cable carries on processing to it, then may reduce the electromagnetic radiation and information divulging effectively.
1 video information divulging mechanism and solution
in 1.1 video information transmission process divulges the mechanism
In computer video frequency circuit, information transmission mainly for parallel transfer and serial transmission two ways. At present the common video information is the serial transmission, in serial transmission’s signal wave length with its video frequency electric cable physics length may compared to the situation, the video frequency electric cable is playing the antenna role, easy to have high strength useful information electromagnetism divulging, like this may realize the receive, the frequency division receive and the position receive easily to the serial signal. Therefore the serial video information is very easy to steal and to reappear.
Under parallel transmission way, because the data line gap is very small, and transmitting message frequency same or similar, therefore the interception difficulty must be much bigger. But R, G, the B three group serial simulated video signal transforms separately after the digital signal, if after processing directly does not carry on the transmission, this time simultaneously transmitted was still a picture element not isotopic information, therefore, considered from the picture element angle, was still the serial transmission. If transmits the image only has the black and white two kind of colors, then on this time parallel transmission electric cable one time data for entire “1″ or entire “0″, namely in the parallel electric cable various holding wires have the same profile, also cannot receive separately to various holding wires, this time the video frequency electric cable is similar to the serial transmission way, the effective information is very easy to steal.
1.2 based on picture element parallel transmission way
To reduce the video signal effectively the possibility which intercepts, in the video signal delivers transmits before the video frequency electric cable to it carries on certain format conversion, enables simultaneously to transmit many picture elements on the parallel electric cable, realizes parallel in the true sense, namely based on picture element parallel transmission. Under this parallel transmission way, even if the receiving end can receive the radiation information, because is unable to distinguish various picture elements the order, also cannot reappear the information.
This article designs against information divulging system is through to video signal format conversion processing, realizes many picture element at the same time transmissions. The digital video signal which when Figure 1 is the video information format conversion principle schematic drawing, the data-in for the serial simulated video signal transforms after A/D obtains, the system receive information, its order is receives in turn according to the single picture element, this time the data is “the picture element package” the form. After format conversion module processing, these the video signal data which the form receives by “the picture element package” is transformed into defers to “the bit plane” the form arrangement output data. This time on the parallel electric cable transmits is many picture element data. “the bit plane” the form video data transmission after demonstrating end returns to original state again through the format conversion module into “the picture element package” the form.
The order receives “the picture element package” the form data to be possible to use the following set way to describe: If the system receives to n picture element, uses D to indicate receives this group of video signal, S expressed in D ordinal response successively between various elements’, the signal color number is 23m plants, namely R, G, the B three kind of colors have the 2m level gradation separately, then:
Similarly, transforms after “the bit plane” the form output data may also use the similar set way to carry on the description: After E expresses a format conversion image data, F expresses in E ordinal response successively between various elements, then:
By gathers the form which the video information D indicates to transform by gathers the form which E indicates, transmits the work which the data format transforms must complete, namely the request first outputs all picture elements the first binary data, then output all picture element second binary data, until final output each picture element last binary data. Therefore, “the bit plane” the data is n picture element three kind of color, has “the weight” same the data set.
2 system hardware designs
2.1 overall concept design
Picture element parallel transmission principle which proposed according to above, designs based on the FPGA against video information divulging system. Figure 2 is this system hardware design diagram, the overall system is composed of the gathering end adaptive card and the demonstration end adaptive card.
The high speed video frequency special-purpose A/D switch uses AD Corporation’s high performance AD9883A, the main feature is:
(1) reaches as high as 300MHz the band width and the 140MSPS transfer ratio.
(2) three group independent 0~1.0V input signal scope, very suitable sampling video signal.
(3) provides the I2C bus interface and so on, adapts many kinds of applications.
The high speed video frequency special-purpose D/A switch uses AD Corporation’s high performance ADV7125, the main feature is:
(1) reaches as high as 330M the volume of goods handled.
(2) three group independent 8 DA switch.
the (3)TTL compatible input signal, is advantageous for the circuit design.
(4) single power source 5V or the 3.3V power supply, widely applies in the digital video system, the high resolution color image display system.
The system principle of work is: Will come from obviously the card video signal input to the gathering end adaptive card, in the gathering end adaptive card A/D switch R, G, the B three group simulated video signal separately transforms three group parallel 8 digital signals, simultaneously also to the line, the field locking carries on the phase repair and the scope compensation, causes it to become the standard the line, the field synchronizing signal, then delivers this signal to FPGA, simultaneously will transform under state machine’s control take the picture element as unit’s video information into “the bit plane” the form. After signal processing, through parallel transmission electric cable transmission to demonstration end adaptive card, but demonstrated that the end adaptive card will be responsible for “the bit plane” the information return to original state into the picture element form, and will give through the D/A switch three group altogether 24bit digital video signal reduction simulated signal the graphic display device to carry on the demonstration.
2.2 electromagnetic compatibility design
2.2.1 signal integrity design
In the system the digital video signal to transmits the latency request to be high, when wiring, it walks the line the way to roughly and identically as far as possible short, realizes to transmits the latency request; The possible arrangement decoupling electric capacity places the position, approaches as far as possible must carry on the decoupling the power source; Around the AD9883A chip and the ADV7125 chip electric circuit’s wiring must be as far as possible short, the periphery primary device must arrange as far as possible compact, reduces the current loop area, thus reduces the electrostatic disturbance; When has laid aside the hole, pays attention do not be excessively dense, in order to avoid damage mirror image level; The adaptive card uses the resistance, the electric capacity, the inductance and the IC chip is the superficial placard installs the part, is advantageous in suppressing the electromagnetic interference.
2.2.2 power source integrity design
The system uses a/D switch chip, the D/A switch chip have the strict request to the power source, except must have the simulation power source and the digital power source particularly, AD9883A must have the PLL electric circuit’s special power source, but the FPGA power source must have the essence power source and the digital output pin power source. Therefore, overall system’s power source design is a very major problem. Here takes FPGA with two piece of LT1764 two kind of power sources, takes AD9883A with two piece of TPS76333 two kind of power sources, piece of TPS76333 takes ADV7125 the power source. Two adaptive cards use four plywood structures, the top layer and the first floor walk the line level as the signal, the intermediate level respectively are the stratum and the power source level, guaranteed system when high speed movement has the good power source environment.
3 system logics realize and the simulation
The FPGA chip uses Altera Corporation Cyclone series chip EP1C6Q240C8. The Cyclone series chip is based on 1.5V,0.13μm the craft, has clock phase-locked loop (PLL) and the special-purpose DDR connection, supports many kinds of I/O standards the chip. Its internal has inserted many special-purpose hard core modules, widely uses on the programmable piece in system (SOPC).
This system carries on processing to the high speed image signal, works clock near 100MHz. In order to obtain the better wiring effect and the system performance, the clock signal must arrive at the overall situation clock wiring network after the phase-locked loop. This design establishes Cyc lone using Altera Corporation’s Maga Wizard the PLL parameter to produce IPcore, has solved the signal latency problem, simultaneously has also satisfied when the read video signal needs the establishment, maintains the time request. Figure 3 is uses FPGA internal PLL carries on the phase-shift after input spot frequency clock PXCLK_AD the profile, in the chart, pxclk with frequency frequency, after phase repair and scope compensation serves as the system datum clock, delayclk is the frequency three frequency divisions, serves as the time delay clock.
3.1 video information format conversion module
In the gathering end adaptive card, the video information by “the picture element package” the format conversion for “the bit plane” the form, may complete by a n×m matrix switching circuit, its input data bus width is m, the output data main line width is n. When system work, each time must carry on n input continuously, namely reads in n picture element the data, carries on m output continuously again, namely writes about these data the respective storage location which the m units place plane corresponds. Format conversion circuitry as shown in Figure 4, uses a n×m D trigger array, in addition the corresponding input and the output lock save the electric circuit and the state machine control circuit, then realizes the nxm data format transformation.
When ith picture element input, the data-in state machine triggers the ith line of D trigger, the ith picture element’s jth gradation information is saved trigger a (i=1,2,…, n, j=0,1,…, m-1), n picture element input completely after ith line of m-1-j in the D finishes, n×m the position binary message completely saves in n×m the D trigger. This time, what in the ith line of D trigger saves is the ith picture element m gradation information, namely “picture element package” form information, what in the jth row D trigger saves is n picture element m-1-j position gradation information, namely “bit plane” form information. The output data state machine outputs in some row D trigger according to certain order the data, then realizes “the bit plane” the data output. The video information the format conversion the form principle is similar by “the bit plane” for “the picture element package” with the above matrixing circuit, as space is limited no longer introduced in this.
In the resolution for 1024×768, refurbishing rate is in the 75Hz situation, selects the frequency is 78.75MHz, because data transmission’s speed and the transmission figure are in reverse proportion, if n
3.2 synchronized signal time delay module
The synchronized signal is certain frequency pulse train, with the video signal existence strict synchronization relations, its frequency concerns with obviously the card hypothesis’s demonstration resolution and screen refurbishing rate. In carries on the video information format conversion process, video information altogether time delay approximately nine spot frequency cycle. In order to enable the video information entered when the graphic display device with the line, mutual succession relations between the field synchronizing signal still to maintain complete, the line, the field synchronizing signal must carry on processing through the time delay module. Figure 5 is in the gathering end adaptive card the good synchronized signal time delay circuit diagram. This system is composed of two adaptive cards, in two adaptive cards the line, the field signal delay circuit is similar.
3.3 system top layer module
After the entire against video information divulging system design completes, its top layer module like chart 6 and shown in Figure 7. In the chart, SCI, SDA used for the initialization AD9883A chip, DATA_RDY are finish the signal from the definition video information transformation.
In two adaptive cards has the format conversion electric circuit, after the video information underwent two format conversions, finally returns to original state into initial “the picture element package” the formatted data. Takes entrance point frequency PXCLK_AD is 78.75MHz, II carries on the synthesis and the succession simulation after Quartus, two top layer module synthesis simulation’s result as shown in Figure 8, in the chart, three groups of data are in turn “the picture element package” the form, “the bit plane” the form, “the picture element package” the form.
Might see after Figure 8 the video information underwent two transformations by the reduction primary data, the line, the field signal correspondingly was also had certain time delay, and maintained with the video information the good synchronism, this explained that based on the picture element parallel transmission way was feasible.
In uses the DMD monitor to take under the terminal graphic display device’s premise, take scene programmable gate array (FPGA) as the foundation, take can realize many picture element at the same time transmissions based on the picture element parallel transmission way as the core computer against video information divulging system, the receiving end is extremely difficult from the receive to the radiation information in distinguishes various picture elements the demonstration order, also cannot reappear the information, thus prevented the video information to intercept effectively, strengthened the information security.
