As a result of the stricter power loss limit, the standard and the standard request, when does the system designer compare now pays attention to the power loss question. Regarding next generation’s design, the power loss budget usually is under the stable control, or reduces, but actually increased more characteristics and the handling ability demand. Usually, although the product characteristic and the performance demand increase unceasingly, the power loss budget is very intense, the function and performance increase with reduces the power loss the goal is contradictory. The mole of law effect reduced the craft size to enlarge the power loss question, moreover, because high transistor divulging increased the static power loss.
Like the digital camera, grasps the equipment, the intelligent telephone and the multimedia player these battery power supply application growth wireless, impelled to the low power loss semiconductor device’s demand. This kind of demand’s paroxysmal growth adds it the request which enhances unceasingly to the energy conservation, specially with the battery life related energy conservation request, causes to the low power loss Semiconductor Technology global demand. Its result is, the semiconductor designer starts to study how to increase under system’s power condition, enhances the performance, to reduce the cost and to lengthen battery’s life unceasingly.
Needs to lower the power loss the Semiconductor Technology application to be possible to be the battery power supply electric appliance, has the reliable consideration heat sensitive application, or has the strict power budget as well as the cooling method the alternating current power supply application which limits. Needs to lower the power loss solution the application including from the portable electronic products to the industry test and the measurement equipment, as well as transportable medical service electronic installation and automobile application as well as military and aviation application.
Regarding these applications, may cause the system to enter and to withdraw from the low power loss pattern fast, obtains the lowest power loss finally and the very long system idle time. Other considerations including the design security, the prototype establishment, the external dimensions, the design multiplying as well as the scene may promote ability.
In the tradition, specific IC (ASIC) and complex programmable logical component (CPLD) has solved the portable market demand. However, in certain low power loss application uses now CPLD starts to lose its charm, because this mainly increases, needs the extra logic to the high-end characteristic demand as well as the relatively high cost causes. Because the product appearing on the market time is longer, and in satisfies the standard which as well as later period’s design changes unceasingly revises on lacks the enough flexibility, uses ASIC the risk becomes higher, is not suitable frequently regarding certain portable applications, these application’s market dynamic change causes to favor in uses the low power loss PLD and FPGA.
As the matter stands, reduces, the competition aggravating as well as the product going on the market time along with the terminal product life has the enormous influence to the product success, the programmable semiconductor platform becomes the first solution. Uses the programmable solution is easiest, and quickest going on the market, profit. However, these programmable platforms should also possess other design requirements satisfiedly, for example cost, function and performance, size, security, as well as inevitable power question. Market research firm iSuppli forecast that 2,000,000,000 US dollar ASIC markets possibly have 300,000,000 US dollars minute volumes to shift to the low power loss scene programmable gate array (FPGA) solution.
Programmable, entire function FPGA, for example based on dodges Actel which saves the IGLOO series to be able to satisfy portable application market the short product life cycle and the keen competition question. These components can meet the portable application design need, for example realizes the highest design security, the small product size by the ASIC level’s unit cost, on the electricity namely with (LAPU), the short product going on the market time, causes it to become ASIC and the CPLD most attractive substitution product. Programmable single chip series static power loss merely 5? W, compares with its closest competitive product, the static power loss reduces 4 times, compares with the leading programmable logical component, the portable application may realize surpasses 5 time of battery lives, has established the new range pole for the low power loss.
In order to realize such low power loss, simultaneously maintains the FPGA content, this series has used the Flash*Freeze technology, allows the component to enter and to draw back the favorable balance of trade low power loss pattern (as shown in Figure 1).
Chart 1:Actel the IGLOO series has used the Flash*Freeze technology, allows the component to enter and to draw back the favorable balance of trade low power loss pattern.
The IGLOO component amount’s part cannot shut off I/O or the clock, simultaneously maintains the design information, the SRAM content and the register. The Flash*Freeze technology with unifies in the system programmable characteristic, permission user in manufacture later period or in application very quick, easily promotion and renewal design. Supports the 1.2V essence voltage also to be possible to further reduce the power loss, thus obtains the lowest overall system power loss.
The Flash*Freeze technology permission user lets all connect this component’s power source, I/O and the clock is at the normal active status. When the component enters the Flash*Freeze pattern, the component will shut off the clock as well as to the FPGA essence input automatically; When the component withdraws from the Flash*Freeze pattern, all activities will restore, the data obtains the retention. This kind of low power loss characteristic adds the programmable characteristic, the single chip, the univoltage and the small size, causes the IGLOO component most to suit the portable electronic products.
Carries on the design through very many methods to cause the available power maximization, may use other low power loss pattern. The low power loss activation function (static free time) permits the component through maintains in the system I/O, SRAM and the register as well as under the logical function condition, carries out function at the same time completely normally, maintains the ultra low power loss. This allows the component to act according to the external input management system management system power loss (i.e. scanning keyboard drive), but the power loss is lowest. Or, under sleep pattern, when FPGA essence voltage shutdown, a bigger equipment may realize the biggest power loss to save. This kind based on dodges the solution on electricity available unique feature which saves, may cause the system to awaken fast from the sleep pattern.
Moreover, looks like the digital camera, the intelligent handset and the MP3 player such hand-hold equipment usually uses the high-end the embedded processor. These embedded processors need work together with one kind or several kind of commonly used memory interface, for example IDE, CE-ATA, SDIO or CF. Therefore, the urgent need effective memory interface management, unloads the processor responsible these duties to low power loss programmable FPGA. These components may manage VLIO or between the AMBA main line and the different kind of memory’s connection very easily.
This article subtotal
More and more strict power loss limit, the standard and the standard have established a hoop-tightening incantation for the system total power loss, the system designer faced with more and more big challenge. In addition, terminal product need more functions and higher handling ability, these can cause the power loss increase, but is not reduces. Based on dodges entire function programmable FPGA which saves more and more to become the portable market the first choice solution. These appear newly the product satisfies the portable market strict design requirements, for example by the ASIC unit cost, obtains the low power loss, the biggest design security, the small external dimensions, on the electricity namely with as well as the fast appearing on the market advantage, becomes traditional ASIC and the CPLD solution had has attracted alternative scheme.
