64 Kbit/s A laws or Mu the law logarithm pressure expands the PCM code obtained the widespread application in the large capacity fiber optic communications system and the digital microwave system, but because takes the big transport tape to have the complex framing structure affable, the PCM code does not suit the wireless phonetic system’s application. The continuous variable slope increase (Continuously Variable Slope Delta, CVSD) modulates by it low application difficulty, the cost and the code rate, the good pronunciation quality widely applies in the tactical communications network, the satellite communication, the blue tooth and so on wireless speech transmission domain. In recent years FPGA developed unceasingly evolves, and had the remarkable enhancement in the skeleton aspect in view of the DSP application. These enhancements enable FPGA to be able to support various domains the numerous complex DSP application, like the telecommunication (base depot signal processing, radar signal processing and so on), multimedia processing (video processing, tonic train signaling processing and so on) and other application domain, the author unifies FPGA the flexibility, formidable digital signal processing ability, the short development cycle, proposed based on FPGA 32 Kbit/s the CVSD pronunciation codec encoder-decoder.
1 CVSD principle
Delta modulation (Delta Modulation, DM) with a code expression neighboring type value relative size, thus reflected the sampling time profile the change tendency, it divides into the linear delta modulation (Linear Delta Modulation, LDM) and the auto-adapted delta modulation (Adaptive Delta Modulation, ADM). In LDM uses the fixed quantification stair △, will cause two kind of distortions in the quantification code’s process, one kind will be the slope overload distorts, it will be because quantification stair △ too small, will not be able to follow in the waveform the slope steep part to create, another kind will be the pellet distorts, it will be because quantification stair △ oversized, will create in the waveform slope small part. CVSD is one kind of auto-adapted increase ADM algorithm, dynamic alignment quantification stair △ size along with input signal change, when the input signal scope rate of change increases, the quantification stair increases correspondingly, when the input signal scope rate of change reduces, the quantification stair reduces correspondingly.
2 CVSD arranges the decoding algorithm
2.1 encoding algorithms
Encoding algorithm flow as shown in Figure 1, x(n) is the input pronunciation sampled signal, sampling frequency fs=32 kHz, xp(n) is the first-order predicted value, d(n) is input sampled signal x(n) and the first-order predicted value xp(n) differential value, Beta for quantity step attenuation factor, △0 for initial quantity step. Module L realizes the level switch, inputs when c(n)=1 the output is 1, inputs when c(n)=0 outputs for - 1, therefore the module L value of exports is 2c(n)-1.
When x(n)≥xp(n), d(n)≥0, the code outputs c(n)=1, when x(n) 
2.2 decoding algorithms
Decoding algorithm flow as shown in Figure 2, it is the code counter process, because the integrator outputs xQD(n) is a step wave, has the high harmonic component, here through a digit low pass filter smooth integrator’s output. When c(n)=1, xQD(n)=xQD(n-1) △(n); When c(n)=0, xQD(n)=xQD(n-1)-△(n). And measures step △ (n) the value with the encoding algorithm.
3 FPGA designs and realize
3.1 parameter designs
CVSD arranges in the decoding algorithm to involve to the quantity step attenuation factor Beta, the initial quantity step △0 and the low pass filter coefficient design. Measures the step attenuation factor to satisfy: β=1-T/τ, T expresses the voice signal cycle, voice signal frequency f=300~3 400 Hz, therefore cyclical T=0.29~3.30 ms, Tau for syllable time-constant, in ordinary circumstances τ=5~10ms. △0 the selection is very important, if △0 the selection is too small, will cause an initial period of timing sampling between the digital signal and the input signal has the big distortion, needs to pass through the long time to be able to track on the input signal, to reduce the pellet distortion and the overshot distortion, will correspond the organization standard according to Europe, will unify the multiple MATLAB simulation test, will take β=0.855, △0=0.043, as shown in Figure 3.
Rises the cosine window to have good side-lobe cancellation and the stop-band weakens, the digit low pass filter designs 14 steps to rise the cosine window limited pulse response (Finite Impulse Response, FIR) the filter, because its parameter sampling rate fs=32 kHz the voice signal frequency spectrum concentrates in 300~3 400 Hz, the digit low pass filter pass band cut-off frequency design is fc=4 kHz/32 kHz=0.125, FIR filter coefficient vector B= [0.0029 0.0086 0.02600.058 0 0.1000 0.1400 0.1645 0.1645 0.1400 0.1000 0.058 0 0.0260 0.008 6 0.002 9]. As shown in Figure 4, because the signal passes through 14 step FIR low pass filter, the output signal and the original sampled signal compare existence certain time delay, after low-pass filtering the original signal obtained the good restoration.
3.2 CVSD codec encoder-decoders
When hardware design uses the design method from the top, divides into each kind of functional module the codec encoder-decoder. The CVSD encoder is responsible to process sampling frequency 32 kHz the sampling 16 bit voice signal, by the comparison decision module, three joined mark examination module, the quantity step adjustment module and the predicted value has the module to be composed, hardware architecture as shown in Figure 5. Has compared with the decision module the predicted value the predicted value which and the voice signal value the module produces carries on the comparison, if input voice signal value >= predicted value, then code output “1″, otherwise code output “0″. The code inputs three joined mark examination module to carry on three continually levels the decisions, the through-put step adjustment module and the predicted value has the module to produce the dynamic quantity step and the predicted value. And the predicted value has the module to need to pay attention prevents the data overflow.
The CVSD decoder is responsible to process 32 kHz the single bit marks, according to Figure 2, coded in the process the predicted value production module already to realize the decode procedure, the behind digit low pass FIR filter has used the distributional algorithm (Distributed Arithmetic, DA) to carry on the design, enhanced enormously while the accumulation operation potency, and has saved the FPGA hardware source. The decoder also needs to design a clock to have the module, because uses the distributional algorithm 14 step low pass filter’s clock rate is data clock’s 16 times.
4 simulation tests
Uses Quartus Ⅱ6.0 carry on the development simulation, the verilog language programming. For ease of the software simulation, designed the DDS supply oscillator, the CVSD encoder’s input has provided by the sine supply oscillator DDS module. Simulation result as shown in Figure 6.
Finally development board has carried on the hardware test in Altera on the DE2, the chip is Cyclone II EP2C35, the codec encoder-decoder hardware source consumption see Table 1. A/D input simulation’s voice signal, sampling frequency 32 kHz, the sampled signal after the encoder, the decoder, the low-pass filtering again through the D/A transformation output decoding’s voice signal, as shown in Figure 7. The test result indicated that the output voice signal is ideal, the showing design is feasible.
5 concluding remark
CVSD is one kind of auto-adapted increase PCM, has the very strong robustness to the error code, excels to process the loss and the pronunciation sampling which damages, the encoder is the single bit code, compares with PCM does not need the complex framing equipment, and in the decoder integrated the digit low pass filter, causes to arrange the decrypt device to be simple, synthesizes these superiority, the CVSD especially qualify applies in the wireless voice communication system, has the very broad application prospect.
