In some control signal processing system, selects ADSP-BF561 to take master control machine, the external connection keyboard, the LCD display monitor, the standard RS232 connection, the real-time clock and so on, realizes through the DSP programming to each functional module control, simultaneously produces the multi-channel digital IO signal. This control system also includes the power source, the clock, CPLD, the FLASH, JTAG debugger, the reset circuit and so on basic building block, system diagram as shown in Figure 1. 
Figure 1 based on ADSP-BF561 control signal processing system diagram
The system power source module selects TPS54350 to realize, the peripheral circuit different RC value, may constitute the different output voltage, what here needs to produce is 5V, 3.3V, the 1.25V three kind of voltages. The clock circuit realizes by the 48MHz crystal oscillator electric circuit, its output takes DSP the periphery clock and the CPLD clock. FLASH uses in saving the user the application procedure, the JTAG debugging mouth in the DSP circuit design is also essential. Latter 11 introduced facing each part that specially to the reset circuit, the digital IO signal’s production, as well as the RS232 connection carries on the detailed introduction.
1. Keyboard
What the keyboard selects is 4×4 the scanning keyboard, as shown in Figure 1, realizes by Blackfin GPIO connection PF5~PF12. And, KEY_GP3~KEY_GP0 is the good line input end, the initialization to take to bring with pulls the resistance the input port, the interrupt enables (drop along triggering); KEY_GP7~KEY_GP4 is the alignment out-port, the initialization to output the low level. The keyboard scanning method same convention’s scanning keyboard method is the same.
Figure 1 Scanning keyboard structure drawing
2. LCD display monitor
The LCD display monitor uses 320×240 the LCD liquid crystal module. the 320×240 liquid crystal module uses for parts the sed1335 actuation to meet the oral plate, the sed1335 actuation meets on the oral plate to use for parts 32K RAM. LCD controls besides the read-write holding wire by the Blackfin read-write signal, 8 bit data lines save the output by the Blackfin low 8 bit data line lock, as well as it enables the signal by the Blackfin AMS3 control, the LCD allocation is 0×2C000000. Electric circuit connection as shown in Figure 2. When carries on the control to LCD, besides must establish the Chinese character which and English fonts demonstrated on LCD, but must compile to the sed1335 first floor driver. This may in the LCD bringing driver foundation, carry on the code transplant, rewrites it suits BF561 the DSP procedure.
Figure 2 LCD connection schematic drawing
3. real-time clock
Control system’s real-time clock selected chip DS1337 to realize. DS1337 is a low power loss serial real-time clock chip, it has 24h/12h to make two kind of patterns, it may output the year, the month, Japan, divide, a second form. It uses the I2C agreement, Blackfin PF0 and PF1 takes I2C CLK and DATA, but PF3 takes real-time clock’s interrupt FLAG, its electric circuit connection schematic drawing as shown in Figure 3.
Figure 3 real-time clock electric circuit connection schematic drawing
4. reset circuit
In order to guarantee DSP or presses down when on electricity repositions the key can the reliable replacement, generally a Canadian replacement delay circuit, selects MAX708S to complete, as shown in Figure 4.
Figure 4 reset circuit
On electricity process, RESET signal after VCC will achieve the regulated voltage in period of time (approximately 200ms) will maintain for high, will then change low again. The signal is RESET “NOT”, after namely meets relative VCC time delay period of time, changes high again, as shown in Figure 5. Thus, in DSP various supply voltage already stable situation, DSP reset signal still for low effective, may guarantee DSP the normal replacement.
Figure in 5 on electricity process signal
After on electricity, if manual presses down the switch, causes on MR the signal by high -> low -> high, produces a low pulse, on the base pin also will output by now a low pulse, was only the time which its low level continued compared to MR on about low level duration long 200ms, guaranteed that DSP the replacement completed reliably, as shown in Figure 6.
Figure 6 time hand reset signal
5. Digital IO signal production
In this control system, the request produces 8 group digital IO signal. If regards as these 8 group digital IO signal 8bit the number, then must produce a limited length non-square-wave coded signal, the following chart shows. The digital IO signal which needs to produce in the T0 time is STAT0, for example 10010101; In needs to produce STAT1 in the T1 time,…, needs to produce STATn in the Tn time, moreover T0 was not possibly equal to that T1 or the Tn, STAT condition is also various.
Figure 7 digital IO signal condition
Here selects BF561 the watch-dog timer (Watchdog Timer) to realize. In the watch-dog timer’s operation, will count the value to read in first register WDOG_CNT, then the watch-dog timer reads in automatically the WDOG_CNT value register WDOG_STAT. Then enables Watchdog Timer through register WDOG_CTL, the watch-dog timer to start to count, reduces WDOG_STAT gradually the value, until is 0, by now compiled in advance the program event will occur. Must want to output 8bit the data, only need write the number toward some address unit, the corresponding data line will write this data. To maintain this data period of time (the Tx length), but must use the latch to lock in this data. Therefore has defined the digital IO signal correspondence interruptive event first in the BF561 DSP procedure, and the interrupt priority is high, this is to guarantee that the precision fixed time, prevents other event disturbance.
register_handler (ik_ivg9, DIO_WDOGA_ISR);
Then in the interruptive event, the data which current must read in writes on some address unit, then enables Watchdog Timer, reads in again timer’s value in WDOG_CNT. Timer’s counting is take sclk as the datum, the procedure code is as follows:
*pDIO_Data_Port = codes;
*pWDOGA_CTL =DISABLE_WDOG;
*pWDOGA_CTL |=WDOG_EXPIRED_BIT;
*pWDOGA_CNT =times;
*pWDOGA_CTL = ENABLE_GPI;
codes and times are the digital IO code which and the length current must produce. Because is a series of codes, may use the array index the form, the current value will read. But we define DIO_Data_Port the address are 0×24000000 beforehand, this corresponds BF561 AMS1 the address space, therefore enables the signal with AMS1 as the latch, will again later output the data line in data through the latch, the following chart will show
Figure 8 Digital IO latch
6. standard RS232 connection
In order to let between the control system and the computer may carry on the data the mutual transmission, the system uses the MAX3232 chip to realize, as shown in Figure 9: 
Figure 9 Between BF561 and computer’s serial port correspondence diagram
BF561 UART follows the asynchronous serial communication agreement, including: 5-8 data positions; 1st, 11/2, 2 stop position; Has/the non-odd-even check. But the baudrate satisfies
And, SCLK is the DSP system’s clock rate, the Divisor value is situated between 1~65536, may corresponding be worth from the timer register, satisfies the relationship
In the BF561 initialization establishment, supposes UART is the 8bit data pattern, simultaneously the Timer2 establishment is the WDTH_CAP pattern, catches the serial port data rate of change with Timer2, but Timer2 located at the TMRS8 register, the procedure initialization code is as follows:
*pUART_LCR = WLS(8);
*pUART_MCR = LOOP_ENA;
*pTMRS8_DISABLE = TIMDIS2;
*pTMRS8_STATUS = TRUN2 | TOVL_ERR2 | TIMIL2;
*pTIMER2_CONFIG = TIN_SEL | IRQ_ENA | PERIOD_CNT | WDTH_CAP;
*pTMRS8_ENABLE = TIMEN2;
*pUART_GCTL = UCEN;
In the procedure, will defer from the very beginning to the initialization establishment to carry on the automatic baudrate examination. When has the character input, timer will survey the continual 2 drops along the width, and will return to the period register which will correspond to timer. When for example, transmits” @” (0×40h) takes the automatic baudrate examination, the transmission including the outset position, altogether is 8bit, as shown in Figure 10. 
Figure 10 automatic baudrate examination character” @” (0×40h)
Here period size like figure above shows, capture UART bits is 8, therefore obtains
According to the baudrate formula, may obtain the baudrate again the size. This section of procedure code is as follows:
Period = *pTIMER2_PERIOD; // returns to period the value
Divisor = Period >> 7; // right lateral 7bit quite in dividing 16×8
BaudRate = SYSCLK/16/divisor; // obtains the baudrate
Conclusion
The entire control system is take the LCD demonstration contact surface as a foundation, carries on the corresponding keyboard operation according to the prompt. After the test, this system various part of work are normal, do not have disturb the phenomenon mutually. The real-time clock is fixed time precise, may achieve a second level. The digital IO output’s profile code does not have the additive device, the timing precision may reach a millisecond level. When RS232 connection transmission data, reaches as high as 115200bit/s the baudrate transmission, the error rate is smaller than 5%. This control system has succeeded applies in some radar system’s control subsystem.
