Abstract: This article designed realizes one kind to use in surveying the baseband to transmit channel’s error code meter, elaborated the main module’s principle of work, proposed one kind of new integral phase demodulation synchronized clock withdrew realizes the method, this method could enhance synchronized clock’s accuracy, thus increased the error code measuring accuracy.
Key word: Code error tester; FPGA; Discriminator; Digital phase-locked loop
Introduction
The error code meter is appraises the channel performance the preliminary survey instrument. This article introduced the error code meter unifies FPGA the characteristic, uses the brand-new integral phase demodulation structure, proposed one new error code test method, after tests the confirmation many times, the plan is feasible, the design system is stable. This article designs the error code meter is composed of two parts: Sending set and receiver.
1 sending set
Sending set’s major function is produces has the stochastic characteristic pseudo-random m sequence, realizes through FPGA by the VHDL programming. The pseudo-random sequence has the principle to be as follows:
Figure 1 the pseudo-random sequence has the schematic diagram
And, ak-i is each shift register’s condition, Ci corresponds various registers’ feedback factor, is 1 expression participation feedback, is 0 does not participate in the feedback. The feedback transfer function is:
When progression n and feedback factor, once determined, then the feedback shift register’s output sequence has determined, a m sequence’s important nature is: Any m sequence’s end around shift was still a m sequence, the sequence length is m = 2n-1.
2 receivers
The receiver mainly by the clock synchronization module, the condition synchronization module is composed, its function diagram as shown in Figure 2.
Figure 2 error code receiver function diagram
2.1 clock extraction module
This unit uses the clock extraction method is uses the new integral phase demodulation to realize, through carries on the integral in a clock cycle to the element, the judgment lags in advance, thus enormous reduced the possibility which, because unwanted signal’s appearance causes to move by mistake. The clock withdraws the schematic diagram is as follows:
Figure 3 clock extraction schematic diagram
(1) discriminator
Before leading, - the lag digit discriminator characteristic is, it outputs an expression local to estimate the signal in advance or the lag in the input signal quantity. If local estimates the signal in advance in the input signal, then outputs “in advance the pulse”, with the aim of using this “the pulse the control local to estimate the signal the phase to retard in advance”. Otherwise, then outputs “the lag pulse”, and causes local to estimate the signal the phase to move ahead. Before leading, - the lag digit discriminator to be possible to divide into the differential form and the integral two kinds. Because before the integral leads, - the lag digit discriminator, has the fine resistance to interference. Before therefore this design used the integral to lead, - the lag digit discriminator.
Before the integral leads, - in the lag digit discriminator, the local clock’s rise along for the synchronism integral’s clean time, when rises along the arrival, under the local high frequency clock, the synchronism counter starts to count, when the input element is “1″, comes a radio impulse counter to add 1 counting every time, when the input element is “0″, comes a radio impulse counter to reduce 1 counting every time. When immediately a rise along arrival, will count the value output, and resets the counter, the counter makes a fresh start under the radio impulse to count. Local clock’s drop along for phase integral clean time, when drop along arrival, under the above same high frequency clock, the phase integral counter starts to count, when the element is “1″, the counter adds 1, when the element is “0″, the counter reduces 1. When immediately a drop along arrival, will count the value output, simultaneously to the counter reset, counts. In the accurate synchronization’s situation, the synchronism integral’s integrating range is just right and a receive element width superposes, the synchronism integral counter output for ± T ( T expression element is 1,-T expression element is 0), but the phase integral output is 0 or ± T. in the phase integral cycle, if the element presents 0→1 or 1→0 the change, then the phase integral output is 0. In phase integral cycle, if the element has not turned over, the element is throughout “1″, then the phase integral counter output is T. If the element is throughout “0″, then phase integral counter output for - T. If local estimates the clock in advance in the input element, when the synchronism integral counter’s output is bigger than 0, then afterward phase integral counter’s output is also bigger than 0, when the synchronism integral counter’s output is smaller than 0, then afterward phase integral counter’s output is also smaller than 0. When the synchronism integral counter output is T or - T, when afterward phase integral counter output also for T or - T, indicated that is at the company “1″ or the company “0″ the condition, then or the lag symbol is 0 in advance. If local estimates the clock lag in the input element, when the synchronism integral counter’s output is bigger than 0, then afterward phase integral counter’s output is smaller than 0, when the synchronism integral counter’s output is smaller than 0, then afterward phase integral counter’s output will be bigger than 0.
When drops along the arrival, examines the synchronism counter the first output, when is 0, if the counter output is 0, then expressed that has not started to examine, does not have in advance the lag information. If the counter output is not 0, then expressed local estimates the clock just with treats the examination the clock orthogonal, is in advance with the lag dividing line place, does in here to it processes in advance. If the synchronism counter’s output is not 0, if this time the counter output is 0, then expresses just two clock synchronizations, therefore does not have in advance with the lag information. If counter output for earth 20, namely for entire element length. Then expressed that the counting process is throughout “1″ or “0″, presents the company “1″ or the company “0″ the condition, to prevent the misoperation, similarly does not think in advance with the lag. If in this time the counter output is not 0, is also not the entire element, and the counter output’s sign bit carries on the synchronism counter’s output different or, namely both mark same expression in advance, the mark expresses the lag differently.
(2) the double-phase high frequency clock source with stops takes away the control circuit
The double-phase high frequency clock source forms two group narrow signal impulses, two narrow signal impulses just differ 180 degrees. Stops takes away the control circuit mainly by to add the gate and to knock on a door is composed, when comes a in advance pulse, adds to knocks on a door, deducts a crystal pulse, such frequency divider’s output pulse phase has lagged for 1/20 cycle. When comes a lag pulse, adds to adds the gate, the control adds the gate to open, joins a crystal pulse to the or gate. Because adds to adds the gate the crystal oscillator signal with the crystal oscillator signal phase which adds to knocks on a door to differ 180 degrees, when therefore from adds the gate joins a crystal oscillator pulse to the or gate, is equal in is knocking on a door the output crystal oscillator signal middle to insert a narrow pulse, also made the frequency divider input end to increase a pulse, such frequency divider’s output phase has been ahead of time for 1/20 cycle. Thus realizes the position synchronization.
2.2 condition synchronization module
The condition synchronization module mainly includes by the position comparison examination module, the error code statistics and the threshold examination module, the parallel input and the state control module, the condition parallel comparison module, the company “1″ the condition counter module.
(1) error code statistics and threshold examination module: Under clock’s metre, to the error code pulse counting, simultaneously carries on the counting to the clock pulse. If the error code integer occupies the clock integer above 30%, then thought that the error rate is very high, showed the system two sequences the condition synchronizations, this time the threshold detector will not output the low level, needs to carry on the synchronized search. If the error code integer occupies the proportion is low, then outputs the high level, explained that this time the system condition synchronization, no longer has carried on the synchronized search.
(2) parallel input and state control module: When the control end is “0″, this module delivers according to the original design two group of parallel input signals the out-port, when is “1″, will possess the output signal to set “0″. By now the condition comparator’s all input signal electric potential same and output the high level, expresses the system already synchronization, the lock-in synchronism protection condition.
(3)th company “1″ condition counter module: This module’s function has two: First, outputs the company to the condition comparator “1″ the condition to carry on the counting, when the counter counting quantity achieves the establishment value, the counter output is “1″, and controls “the parallel input and the state control” the electric circuit, causes each parallel output position “0″. Thus, the condition comparator’s each input position is “0″, then its output is “1″, expression condition already synchronization; If the condition synchronization, the company “1″ the counter output throughout is not “0″. Including “1″ counter another function is works as when its output is “1″, only then causes the error code counter to carry on the counting. If after overall system already synchronization, presented the condition out-of-step, through error code statistics and threshold circuit’s output state control company “1″ counter. When the company “1″ the integer arrives at the hypothesis the integer the output is “1″, and gives the parallel input and the condition controller, causes its output to set is “0″, realizes the synchronized protection control.
3 concluding remark
This article designs the error code meter’s merit is may the very convenient application transmit channel’s test in the baseband, but the correct measurement baseband transmits channel’s transmission error code, and the cost is low.
