Along with the modern science technology’s development and computer technology’s popularization, the high speed data gathering system has applied in more and more situations, like domains and so on correspondence, radar, biomedicine, robot, pronunciation and imagery processing. This article introduced the data acquisition processing system uses CPLD to control ADS8364 to complete the data a/D transformation, after the transformation data saves in advance to FIFO, passes through after front end again DSP carries on the digital signal processing, through the USB main line passes to the superior machine, and carries on the memory, the demonstration and the analysis in the superior machine and so on. This system definitely may satisfy signal gathering to process to the high accuracy and the timely request.
1 system principle
The data acquisition processing system mainly by the front end signal recuperation electric circuit, ADC chip ADS8364, CPLD chip EPM3128A, DSP chip TMS320F2812, USB chip CY7C68013 and the peripheral circuit is composed. System principle diagram like chart l shows.
The system mainly completes the duty is: The DSP receive superior machine the order which transmits through the USB main line, completes the system operational parameter the establishment, and carries on the correspondence through the simulation address/data bus and CPLD, to CPLD transmission control command; To the exterior multi-channel simulation quantity input clear signal recuperation, carries on the single channel or multichannel A/D under the CPLD control transforms, will gather data storage in a piece of FIFO chip; When in FIFO saves when data half-full, produces a signal of stop to DSP, DSP receives this signal of stop
, takes out in FIFO the partial data, front end carries on the digital signal processing, will process the data which finished through the USB main line to pass to the superior machine; The superior machine realizes each kind of graphical interface operation and rear end the signal processing, to the signal which gathers carries on the analysis. The system may carry on the synchronized sampling to the input multi-channel simulated signal, this enables the data which gathers not only to include the simulated signal scope characteristic, meanwhile maintains between the different simulated signal the differ in phase; The sampling frequency may initialize, adapts the different speed sampling request.
2 system hardwares
System hardware including signal recuperation module, A/D transformation module, DSP processor module, CPLD logical control module as well as USB connection module.
2.1 signal recuperation module design
Exterior multi-channel simulation quantity input signal often is the weak sensor signal, the signal peak-to-peak value is small, to facilitate, and does not lose the generality, supposes its peak-to-peak value scope is O~25mV. ADS8364 waits the transformation the analog input voltage range to maintain between AGND-0.3V and AVDD O.3V. Here selects the low power changes gain measuring appliance amplifier INAl29 to simulates the quantity input signal to carry on the recuperation to enlarge, its enlargement is between 0~5V.
INAl29 is the BURR-BROWM Corporation’s one kind of low power all-purpose instrument amplifier, has the outstanding precision and the very wide band width, reaches as high as 100:00 in the gain, the band width reaches 200kHz. Its available sole exterior resistor adjusts its gain, the regulation band is l~10000, its enlargement factor formula is:
Thus causes the enlargement output voltage between O~5V. Signal recuperation module schematic diagram as shown in Figure 2.
2.2 A/D transformation module design
This module used TI Corporation high speed, the low power loss, six channel synchronization sampling mold/to teach switch ADS8364, it used the 5V working voltage, its 6 analog input channel divided into three groups (A, B and C), each group had ADCs maintains the signal (HOLDA, HOLDB and HOLDC), used for to start each group the AID transformation, 6 channels might carry on the synchronized parallel sampling and the transformation. ADS8364 uses has the 80dB syntype inhibiting ability entire differential input channel, receives the same place its REFin and the REFout pin, provides 2.5V for the difference channel the reference voltage. Here simulates the quantity to use the single end input, - IN front end termination syntype voltage 2.5V, IN termination signal recuperation module output.
The ADS8364 clock signal provides by exterior, the upper frequency is 5MHz, the corresponding sampling frequency is 250kHz. Here provides the clock signal by CPLD, is mainly considered CPLD may change the clock rate nimbly, then change system’s sampling frequency. After a/D transformation completes, produced transformation conclusion signal EOC. ADS8364. The BYTE pin meets the low level, causes the transformation result by 16 way outputs. The address/pattern signal (A0, Al, A2) decided ADS8364 the data read way, may choose way including single channel, cycle or FIFO pattern. Sets at the ADD pin for the high level, causes the read-out in the data to contain the transformation channel information. Considered the data acquisition processing system’s sampling frequency is generally high, if with DSP positive governing ADS8364 visit, will take DSP many resources, simultaneously is also high to the DSP timely request. Therefore in this system design, realizes the ADS8364 interface control electric circuit with CPLD, and will transform the result to save in the FIFO chip, realizes the FIFO chip output interface with DSP.
Between DSP, CPLD, ADS8364 and FIFO connection design as shown in Figure 3.
2.3 DSP processor module design
The DSP primary cognizance and the USB connection module exchange data, simulates the address/data bus’s way and the CPLD correspondence, realizes to the data acquisition control, front end completes carries on the digital signal processing with the FIFO chip output interface as well as after the sampling data (FIR low-pass filtering). Here selects TI Corporation’s 32 fixed-point DSP TMS320F2812 (to hereafter refer to as F2812), it uses 1.8V the essence voltage, has the 3.3V periphery connection voltage, upper frequency 150MHz, internal has 18K character RAM,128K character high speed Flash.
2.4 CPLD logical control module design
In this data acquisition processing system, CPLD is an important constituent. The logical control module which is composed of CPLD receives the movement order which DSP transmits, controls a/D transformation module to carry on the data acquisition, and provides to the FIFO connection succession, realizes the transformation data memory. Here selects Altem Corporation’s EPM3128A chip, it altogether has 128 great units, 2500 available gates.
CPLD takes an independent control to carry out the structure. Through compilation corresponding Verilog the HDL code, then produces the corresponding function circuit, realizes saves, the judgment and processing as well as to each kind of command signal execution and the output signal control to each kind of input signal lock.
2.5 USB connection module design
Here selects in CYPRESS Corporation’s EZ-USB FX2 series CY7C68013 to take the USB communication controller chip, it contains the enlargement mode 8051 micro controllers, supports the USB2.0 transport protocols, simultaneously also downward compatible USBl.1 standard. This chip the USB2.0 transceiver, SIE (serial interface engine), the enlargement mode 8051 micro controllers, the I2C bus interfaces as well as GPIF (general programmable connection) integrates in a body. CY7C68013 has provided SlaveFIFO and the GPIF two kind of connection patterns, Slave the FIFO pattern is from machine the pattern, the exterior controller may look like to ordinary FI
The FO memory carries on the read-write equally to the FX2 multi-layered cushion FIFO memory; The GPIF pattern is the main engine pattern, may establish the read-write by the software the control profile, the flexibility is very big. What here uses is Slave the FIFO pattern.
3 system software designs
System software design including DSP programming, USB firmware program design, USB driver design and superior machine application programming.
3.1 DSP programming
Front end the DSP programming’s primary mission is on the initialization, the management board resources and realizes the digital signal processing algorithm. Here function formidable CCS which provides by TI Corporation (Code Composer Studio) is the integrated development environment. On after system electricity replacement. First completes F2812 own initialization, including disposes the RAM block, establishes the I/O pattern, the timer pattern, the interrupt and so on; Then the procedure enters the person recurrent state, waits for USB and the FIFO interrupt. F2812 master routine flow chart as shown in Figure 4.
Saves the commonly used digital signal processing algorithm in the F2812 program memory, F2812, in receives the superior machine the control information which transmits after the USB main line, chooses some kind of processing algorithm in the interrupt function, simultaneously issues the movement order to CPLD, controls a/D transformation module to complete the data which the signal gathering and will gather to store in FIFO. When in FIFO the data achieves half-full, hands in the interrupt request to F2812, F2812 responds this interrupt, realizes in the interrupt function to the partial sampled data read, completes the data in the main loop procedure according to the superior machine designation’s processing algorithm front end to process, then packs the data, gives the superior machine through the USB main line transmission. Regarding the commonly used digital signal processing algorithm on DSP realization, here no longer gives unnecessary detail.
3.2 USB firmware program design
The firmware is responsible to be auxiliary the hardware to let the equipment two-way alternate data, its major function is: Receives and processes the USB driver the request and the application procedure control command. CYPRESS Corporation series chip has given a Firmware storehouse and the Firmware frame in view of EZ-USB the FX2 (Frame Works), uses Kei the C5l development. The Firmware storehouse provided some constants, the construction of data, the great definition, the function to simplify the user to the chip use. The user only needs in the source program to contain fx2.h, fx2regs.h and fx2sdly.h, and Ezusb.1ib and UsBJmpTB.obj increase income item then. The Firmware frame realized the initialization chip, to process USB standard equipment under request as well as suspended state functions and so on power source management. This frame does not need to increase any code, after will translate, produces the *.hex document writes down the chip to be able to carry on the basic USB correspondence with the main engine, cannot only complete the specific task. In this system, needs to choose the suitable transmission mode, vertex (Endpoint) which the increase needs to use, in the frame reservation’s place (for example functions and so on TD_Init(), TD_Poll()) increases the initialization code and completes the specific function the code.
USB altogether has four data transmission way: The control transmission, the interrupt transmission, the block transmission and the synchronized transmission, in this system used have controlled the transmission and the block transmission. The control transmission mainly uses for to complete the main engine to equipment’s each kind of control operation, namely uses for to realize located at main engine’s on USB main line driver as well as the compilation function driver to equipment’s each kind of control operation; The block transmission mainly uses for to complete mass data transmission as well as carries on the error detection to the transmission data between the main engine and equipment’s (support “wrong of re-transmit” function).
3.3 USB driver design
CYPRESS in the FX2 development package has provided general device driver Ezusb.sys, may use in based on EZ-USB the FX2 series chip, can complete the basic USB communication task. In this system design, has made the revision using DDK to the above driver, not the commonly used function deletion, simultaneously will increase the function which one define.
3.4 superior machine application programming
The superior machine application procedure mainly realizes USB correspondence, the data which transmits to the system transmission control command as well as the receiving system with the data acquisition processing system’s between and carries on the memory, processing and the demonstration. In the Win32 system, each equipment abstracts is the document, the application procedure realizes through the file operation API function with the driver in some equipment’s correspondence. USB corresponds the commonly used API function to have; CreateFile(), WriteFile(), ReadFile(), DeviceloControl(), CloseFile() and so on. In the application procedure, only need increase the above function to the corresponding functional module in then may complete the application procedure to open to the USB equipment, to read, writes and so on operations, thus realizes both’s correspondence. Uses the LabVIEW language to realize the USB correspondence and the instrument contact surface, but realizes and produces the dynamic link storehouse document regarding the rear end signal processing algorithm under the VC environment (*.d11), facilitates LabVIEW the transfer. Figure 5 is the superior machine upper formation application procedure flow chart.
This article unified TMS320F2812 and ADS8364, has designed a set of data acquisition processing system. This system uses the uSB main line and the superior machine correspondence, has displayed USB2.O conveniently fully, the quick merit; Considered to the timely request, certain specific digital signal processing algorithm (for example the FIR filter, fast FFT and so on) puts to the data acquisition transaction card on completes fast by DSP. This system gathering precision is high, the speed is quick, and may simultaneously gather the multi-channel signals. The practice proved that this data acquisition processing system suitably in the high accuracy, the timely signal’s data acquisition and processing, has the widespread use value.
