Abstract: Introduced that one kind based on FPGA design array CCD the component TCDl208AP complex driving circuit and the entire CCD electronic systems control logic succession’s method, and gives the succession simulation profile. The project practice result indicated that this driving circuit structure is simple, the power loss is small, the cost is low, antijamming ability, adaptation project miniaturization request.
Key word: Array CCD; FPGA; Driving circuit; Control logic
1 introduction
CCD (Charge Coupled Devices– charge-coupled device) has the size to be small, the precision is high, the power loss is low, the life is long and merits and so on electronic scanning-self, obtain the widespread application in the image sensing and the non-contact survey domain. Because electro-optical characteristics and so on CCD transfer efficiency, signal-to-noise ratio only then can achieve the best value which under the appropriate succession actuation the design stipulated that output stable reliable signal, therefore, driving circuit’s design also becomes one in its application key questions. The different factory, the different model CCD component’s actuation succession is various, causes CCD the driving circuit very difficult standardization and the production. The author designs is may program again based on the FPGA driving circuit, if must change driving circuit’s succession, increases or reduces certain functions, only need program to the component, in does not change in any hardware’s situation to be possible to realize driving circuit’s renewal.
2 CCD operational parameter and succession analysis
According to engineering project’s specification, this system selects Japanese TOSHIBA Corporation’s TCDl208AP electric circuit to take the sensor. This component has the fine electro-optical characteristic, some 2 160 elements, its driving signal’s succession like chart l shows.
May see by the TCDl208AP succession chart, TCDl208AP uses the two phase drive pulse work, the succession pulse driving circuit provides 4 group work pulses, namely light integral pulse SH, charge transfer pulse φ1, φ2, output reset pulse RS. The system provides master clock frequency CLK is 4 MHz, establishes the data output frequency is 1 MHz. The TCDl208AP model optimum working frequency is l MHz, this component has 2160 effective elements, when normal work must have 52 dummy cell outputs (DUMMY 0UTPUTS) the signal (including dark current signal). Because this component is two rows parallel transmissions, must therefore have 1 106 (2 212/2=1 at least in one cycle 106) a φ1 pulse, namely TSH>1106Tφ1. Moreover, may see by the succession chart, when SH signal for high level period, CCD accumulates the signal electricity purse through shifts the grid to enter the shift register, the shift pulse φ1, φ2 the request maintains Gao an Hedi level condition.
3 FPGA component’s choice
According to the design requirements and the project need, this design selects Altera Corporation Cyclone in the serial products the EPlCl2Q240C8 embedded programmable logic component. EPlCl2Q240C8 uses based on 1.5 V, 0.13μm and the entire level copper SRAM craft, its density increases to 20 060 logical element (LE), RAM increases to 288 KB. It has uses in the special-purpose double data rate (DDR) connection which clock’s phase-locked loop, DDR SDR and the fast cyclical RAM(FCRAM) memory needs, has in the system programmable characteristic. Its collocation method has passive and initiative, the passive disposition is after on electricity by computer after translation produces the sof document use special-purpose downloading electric cable disposition electric circuit. The initiative disposition is after on electricity (EPCS4) carries on the disposition automatically by the special programmable disposition electric circuit to the EP1C12Q240C8 electric circuit.
4 CCD driving circuit design
Driving circuit’s function has the guarantee to produce the CCD component normal work shift clock, to transmit the clock, the sampling maintains the clock, repositions the synchropulse which, the element clock and the clamp pulse the clock, the signal processing electric circuit and a/D switching circuit needs. Only the drive pulse and the CCD good coordination can display CCD fully the electro-optical transformation characteristic, the output stable reliable electro-optic signal.
Before uses the digital logic electric circuit to design the array CCD driving circuit, because uses many counters, the trigger and the gate, the electric circuit is complex, antijamming ability is bad, moreover the succession is difficult to coordinate, is not easy to debug. If uses the FPGA actuation method to produce the driving signal, the system carries on the control with the identical clock to these 4 group driving signal, guaranteed that the definite time relationship, then uses the frequency divider to have the profile which for the clock pulse frequency division each group actuation signal cabin needs, produces the driving signal which as shown in Figure 1 to be much more convenient.
This system’s design uses Altera Corporation’s QUARTUSⅡDevelopment system. QUARTUSⅡThe development system is one kind of complete works Cheng Hua programmable logical design environment, it supports hardware description language (VHDL), the state diagram and the schematic diagram three input mode, functions and so on execution translation, logic synthesis, simulation as well as programming. Design process including 4 stages: The design input, the design realize, the design confirmation and the component programming, as shown in Figure 2. The entire flow is an input, realizes, the confirmation recursive process, is correct until the design and is complete.
Schematic diagram input mode simple direct-viewing, is also most commonly used. If uses the hardware description language input mode like VHDL or Verilog, its probability and the readability are good, but synthesizes the data format document which forms often compared to the schematic diagram input mode to occupy the programmable component’s resources. In order to enhance the chip the use factor, simultaneously uses the schematic diagram input mode also to be possible to produce the new special functional module, in view of the fact that the system scale is not big, therefore uses the schematic diagram input mode to carry on this system’s design. Because TCDl208AP is the two phase drive type, according to the TCDl208AP driving signal’s succession relations, may determine φl=φ2=0.5 MHz, output reset pulse RS=l MHz.
After having determined SH, φ1, φ2 and RS parameter, may according to between them the succession relations design hardware functional block diagram. Each group pulse respectively is RS=1 MHz, the dutyfactor is l:4, the square-wave; φ1=φ2=0.5 MHz, the dutyfactor is 1:l, the square-wave, φ1, φ2 when parallel shift has one to be bigger than SH=1 the wide pulse. In which each module uses the VHDL language to carry on the design, as shown in Figure 3.
After the translation, finally obtains simulation profile result as shown in Figure 4.
5 concluding remark
This design uses QUARTUSⅡThe development system realizes the programming, has completed the electric circuit function design, the succession synthesis and the analysis and the text and the graph input, and needs to download finally according to the project to Altera Corporation’s Cyclone series FPGA in chip EPlCl2Q240C8 produces the CCD actuation succession, not only obtained the good CCD output effect, moreover the big simplified circuit design, enhances the reliability, reduces the power loss, speeds up the research and development speed.
