The abstract proposes and designs one kind new based on the double CPU technology electro-optic pattern recognition system, this system mainly by picture target gathering and the processing module, the electro-optical related union transformation module as well as the automatic diagnosis module is composed. Uses TMS320C6416 and FPGA completes the picture target gathering and processing. Uses ARM9 processor S3C2440 to complete to related power spectrum gathering and the picture target recognition. Compares with the traditional electro-optic pattern recognition system, this system timeliness and the precision are higher, and may realize the intellectualization and the network.
The key word image knowledge hacks electro-optic imagery processing TMS320C6416 the S3C2440 automatic diagnosis module
Introduction
The electro-optical mix pattern recognition becomes by its high speed parallel processing and the non-crosstalk’s merit realizes the pattern recognition practical application and the solid current events’ important way, it in the target identification, the fingerprint recognition, the optical fiber examination, the industry components recognition, domains and so on license plate recognition obtained the extensive research and applies [1.2], and has made the very good recognition progress.
But in the practical application, waits the recognition the picture target to need to undergo operations and so on image pretreatment and distortion processing. In view of the image real-time processing request, this article will unite in the transformation related recognition system and the digital signal processing double CPU technology unifies, the use “FPGA DSP ARM” the construction, studies and designs one kind of new electro-optical mix pattern recognition system. Complete the picture target using TMS320C6416 and FPGA gathering and processing, completes using ARM9 processor S3C2440 to related power spectrum gathering and the picture target recognition, thus realizes the distortion invariable pattern recognition fast and the accuracy. And has realized this system’s intellectualization and the network.
This electro-optical mix pattern recognition system each second can process 25 images, may realize the genuine dynamic pattern recognition, thus has the very good usability to the pattern recognition.
1 electro-optical mix pattern recognition system
The electro-optical mix pattern recognition system is transforms correlation instrument’s one kind of system jointly based on the electro-optical mix, this article proposes electro-optical mix pattern recognition system’s structure diagram as shown in Figure which and designs 1.
ARM9 processor S3C2440 and DSP primarily/from the way, DSP and FPGA asks also primarily/from the way. Picture target gathering which and processing module are composed of DSP and FPGA, will wait the recognition the goal 1 to transmit in DSP through the camera, DSP completes to treating processes and so on picture target pretreatment and distortion processing. Then, after DSP will process picture target and on reference image constitution union input picture real-time output liquid crystal, union image after laser light beam illumination, after Fourier transformation lens 3, forms the union image Fourier frequency spectrum. This frequency spectrum after low-pass filtering, obtains central frequency spectrum [3] which needs, and enters ARM9 through the camera 2 receives processor S3C2440, completes the image frequency spectrum the amplitude modulation and Fourier inverse transformation processing, obtains needs the mutual correlation result. Because the real goal mutual correlation signal is strong, dummy target’s mutual correlation signal is very weak, may judge the genuine and fake picture target through the hypothesis threshold value, namely, when the related result is bigger than the threshold value, recognizes as the real goal, when is smaller than the threshold value, recognizes as the dummy target. When sentences for the dummy target, continues through correspondence interface control DSP to carry on image gathering and processing, realizes the next goal pattern recognition, until distinguishes the real goal.
2 system designs
This electro-optic pattern recognition system mainly by picture target gathering and the processing module, the electro-optical related union transformation module as well as the automatic diagnosis module is composed, uses TMS320c6416DSP and FPGA completes the picture target gathering and processing, uses ARM9 processor S3C2440 to complete to related power spectrum gathering and the picture target recognition.
2.1 TMS320C6416
C64x is the most young blood who TI Corporation promotes C6000 in series DSP, has used the VelociTI1.2 structure, it mainly in internal CPU aspects and so on function unit, general register group and data path has made the big improvement. C64x has 8 mutual independent function units, contains in 6 support monocycles list 32, the pair 16 or 4 8 bit data operation arithmetic logic unit, as well as 2 support monocycle pair of 16×16 position or 4 8×8 bit data operation multiplier; The internal CPU general register group includes 32 32 registers, supports 8 and 64 fixed-point data, and register A0 may also serve as the condition register; The general register group interior has two overlapping circuits, and may visit another one side through the overlapping circuit the register group; C64x can also use the non-arrangement the deposit instruction visit random byte boundary character or the double word.
Compares with C62x, C64x average each instruction increased 7.6 times in each clock cycle’s operational capability. As a result of the C64x support pair 16 and 8 bit data as well as clock rate’s enhancements, caused its imagery processing ability to enhance about 15 times compared to C62x. C64x is the procedure and the address two level of internal memory structures. The first-level memory (L1P) and the data (L1D) buffer is composed of the procedure. And L1P is 512 group of 32B 16KB direct reflection type buffers, L1D is 128 group of 64B 16KB two groups groups unites-like the buffer. C64x has with C621x, the C67lx different storage medium structure, its storage medium located at 32 boundaries, therefore visits regarding the same storage medium time, address bus’s 3LSBs is the same. Moreover, C64x has the rich peripheral device resources, including: 64 channel’s enlargement mode memory direct access (EDMA) controllers; 64 /16 bit data main line’s exterior memory interface EMIFA/EMIFB; 33MHz, 32 PCI connection and in view of asynchronous transfer mode UTOPLA connection; 16 or 32 main engine end connection; 3 multichannel cushion serial port and so on.
Internal structure’s improvement, the parallel processing ability’s enhancement and the rich peripheral device resources, enable C64x to have the huge development potential in the imagery processing domain. In order to enhance the system real-time performance, this article uses basic frequency 400 MHz TMS320C6416GLZ to design this recognition system as the picture target processing unit.
2.2 picture target gathering and processing module
This module mainly and FPGA realizes by DSP processor TMS320C6416, between DSP and FPGA uses main/from the way. And, DSP mainly completes to picture target processing and controls the FPGA sampled signal the start. FPGA completes to the picture target sampling control process, its hardware structure drawing as shown in Figure 2.
Image which photographs from the camera first clear signal recuperation, namely carries on to the image inlays the position, the long spear, the enlargement as well as the synchronized signal separation. Then, starts by DSP to the image signal sampling, namely controls FPGA to carry on the image the sampling, simultaneously through interrupt inquiry way (FTNT), monitors the sampling which FPGA sends out to complete the signal.
Uses TI Corporation’s TLC5510 chip to carry on the high speed A/D sampling. TLC5510 is the 5V power source, 8, 20Msps high speed parallel ADC, the greatest measuring range is 2V. In order to achieve the real-time processing the goal, this system only gathers the gradation image, the CCD image frame frequency is 30Hz, the frame image resolution for 512×512 the picture element, each picture element 0.8 quantifications.
FPGA is an expert to good expert (HS), the field (VS) synchronized signal and under the clock signal actuation, produces a/D sampling control signal to control the sampling process, simultaneously, FPGA provides the memory address and selects patches or strips of land as worth saving for seed with the read-write control signal, the digital signal according to this address and when RAM_W is effective, reads in FPGA in memory RAM, finishes the preparation for the image pretreatment.
After the sampling completes, FPGA has the external interrupt, sends out the interrupt request to DSP, DSP enters the interrupt processing: FPGA provides RAM the address signal, and when RAM_R is effective, DSP reads the RAM in sampled data by the EDMA way to synchronized dynamic memory SDRAM. SDRAM is 4balaks×512 kb×32b, the clock basic frequency is 166 MHz, has like this guaranteed when the work needs storage capacity and timely request. The data transmission finished, DSP started FPGA to carry on the next image the sampling, FPGA enters the sampling control treating processes once more, DSP carries on processing and so on pretreatment and distortion to the picture target data.
In completes after the picture target data processing, after DSP will process, picture target and memory on ROM reference image constitution union input picture real-time output liquid crystal’s agreement region, with the aim of carrying on the optical information processing.
2.3 automatic diagnosis modules
The automatic diagnosis module uses Tristar Corporation ARM processor S3C2440 to complete. The S3C2440 processor is based on ARM920T the essence 32 RISC embedded chip. This ARM the essence CPU basic frequency is highest may reach 533MHz, here uses 499MHz, it besides integrates 3 serial ports, the SD card controller, USB the Host controller, the LCD controller, Nand the Flash controller as well as the real-time clock, but also increased industrial control main line (CAN), the Camera controller (digital camera connection), the PCMCIA connection (to be possible to meet wireless network card or modem and other peripheral devices). Moreover, draws out CPU with 1 96 needle main line slot the local bus, but external connection other main line equipment and with intercommunication. At present, S3C2440 has been widely applied in domains and so on industrial control, multimedia processing, expense class electron and network service.
S3C2440 processor’s connection diagram as shown in Figure 3. S3C2440 built-in Camera controller, and supports most greatly for 4096×4096 the picture element image input, therefore this system selects 1,300,000 picture element cameras to the union frequency spectrum image’s gain to carry on video frequency gathering and the transmission, completes through the Catnera controller to the frequency spectrum image data conversion and the memory, then carries on the amplitude modulation and the inverse Fourier transform to the frequency spectrum, obtains the mutual correlation result, thus carries on the distinction and processing.
In Figure 3, 64MB NAND Flash uses Tristar. K9F1208, uses in depositing the application procedure; 2MB NOR Flash uses AMD AM29LV160DB, uses in depositing Bootloader and Kernel; 64MBSDRAM uses modern HY57V561620; 32KB FRAM (poss ferroelectric random access memory), reduces to the Flash frequent operation, lengthens the Flash life, simultaneously prevents when the power failure data missing.
S3C2440 takes the master control processor, but is also responsible with the superior machine to carry on the correspondence, and may carries on the interconnection through the network card and Internet, realizes this system’s intellectualization and the network. Moreover, but may also carry on the data through the USB connection the deposit.
2.4 system software main flows
This electro-optical mix pattern recognition system work mainstream regulation as shown in Figure 4. ARM and DSP after completing the initialization, through the HPI mouth loads the DSP procedure and through the interrupt activates the DSP movement; DSP after work starts FPGA, FPGA to control a/D sampling chip to carry on real-time image gathering.
3 conclusions
This article studied with has designed one kind new based on the double CPU technology electro-optic pattern recognition system. This system completes the picture target by TMS320C6416 and FPGA gathering and processing, unites the converter through the electro-optic to obtain the image union frequency spectrum related, completes using S3C2440 to related power spectrum gathering and the picture target automatic diagnosis. This recognition system imagery processing ability reaches 25 /s, thus has realized the genuine dynamic image pattern recognition. Compares with the traditional electro-optic pattern recognition system, this system timeliness and the precision are higher, and has realized the intellectualization and the network, has the high use value.
