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Abstract: Analyzes way which and difficulty between the different type monolithic integrated circuit corresponds, proposes one kind of base poss ferroelectric random access memory’s solution and the example. Method which and needs to pay attention including a reliable communication agreement and the flow as well as this method’s merit. Key word: Monolithic integrated circuit correspondence poss ferroelectric random access memory I2C bus arbitration communication protocol Who electronic technology’s swift development, monolithic integrated circuit step like one new time, more and more functions are also varying the monolithic integrated circuit has provided many new methods and the mentality for ours design. Regarding not some situations, for instance: The complex backstage operations and the correspondence and the high timely onstage control system, the software resource consume the big system, function formidable low consumption system, cryptographic system and so on. If uses many kinds of different types reasonably the monolithic integrated circuit unitized designs, may obtain the extremely high flexibility and the performance price compared to, therefore, the many kinds of heterogeneous monolithic integrated circuit system design becomes one kind of new mentality gradually, but between monolithic integrated circuit’s correspondence has been puzzles this method development the subject matter. This article will analyze compares between several monolithic integrated circuit’s ways, the difficulty, and proposes one kind of solution. between 1 several commonly used monolithic integrated circuit’s mailing address ①Uses hardware UART to carry on the asynchronous serial communication. This is one kind takes the mouth line to be few, effective, reliable mailing address; But it is a pity many small monolithic integrated circuits do not have hardware UART, some also has 1 UART, if the system must with superior machine correspondence, the hardware source be insufficient. This method uses in the monolithic integrated circuit having generally should UART, and cannot carry on the serial communication with the outside or use the double UART monolithic integrated circuit’s situation. ②Uses the internal SPI connection or the 2C main line module serial communication form. The SPI/I2C connection has the hardware to be simple, software programming easy and so on characteristics, but the present majority monolithic integrated circuit does not have the hardware SPI/I2C module. ③Using the software simulation SPI/I2C pattern correspondence, ④The mouth suitable parallel correspondence, uses monolithic integrated circuit’s mouth line directly connected, in addition 1~2 handshake holding wires. This way’s characteristic is the communication speed is quick, 1 time may transmit 4 or 8, even are more, but needs to take the massive mouth line, moreover the data transfer is the orbit. In a monolithic integrated circuit transmits 1 byte after another monolithic integrated circuit, after must wait till another monolithic integrated circuit’s receive response signal, can the transmission next data. Generally uses in some hardware mouth line comparison extra the situation. ⑤Takes the buffer correspondence using pair of mouth RAM. This way’s most major characteristic is the communication speed is quick, nearby two may use read-write memory’s instruction direct operation directly; But this way needs the massive mouth line, moreover the pair of mouth RAM price is very high, generally only uses in some having the special request situation to the speed. Looking from the above several kind of plans, each method has the very big request and the limit to the hardware, specially with difficulty realizes on the function simple monolithic integrated circuit, therefore seeks one kind simply, effective, can the method which corresponds between each kind of monolithic integrated circuit have the vital significance.③,④In the plan, the bilateral monolithic confidential transmission each or each byte makes the response, the correspondence data quantity is big when will consume the massive software resource, this requests the high place in some timeliness not to permit. In view of this question, the supposition increases 1 data buffer between the monolithic integrated circuit, large quantities of data read in the buffer first, then lets opposite party take again, each monolithic integrated circuit to the data buffer is the master control pattern, like this definitely will raise the correspondence efficiency greatly. Talks about the data buffering, we will think of parallel RAM immediately, but parallel RAM needs to take the massive mouth line (data line address wire read-write line piece route selection handshake line), generally above 16. This is one digit which lets the human be awed at the sight, will increase the PCB area greatly and brings certain difficulty to the wiring, the extremely few some people will select this method. Serial interface’s RAM is very rare in the market, not only buys moreover the price to be very high with difficulty. The shift register may also make the data buffer, but present capacity biggest also only 128, because is “advanced leaves the structure first”, no matter therefore transmission data how many, the receiving end must move to the entire register, flexibility bad and the large capacity shift register is also rare difficult to buy. One kind is called “the poss ferroelectric random access memory” the chip appearance, has brought the solution to us. 2 take the data buffer’s mailing address using the poss ferroelectric random access memory The poss ferroelectric random access memory is one kind of new nonvolatile storage which American Ramtran Corporation just promoted, is called FRAM. With ordinary EEPROM, Flash-ROM compare, it has does not need the write time, the read-write number of times infinite, has not distributed the merit which the structure may write continuously puts, therefore has RAM and a EEPROM pair of characteristic, moreover the price is relatively low. Now the majority monolithic integrated circuit systems provide serial EEPROM (for example 24CXX, 93CXX and so on) to use for to save the parameter. If replaces original EEPROM with 1 piece of FRAM, enables it both to save the parameter, and can make the serial data correspondence the buffer. 2 (or many) the monolithic integrated circuit meets Cheng Duozhu with 1 piece of FRAM - from the I2C main line way, increases several handshake lines, then obtains the simple highly effective correspondence hardware circuit. In software aspect, so long as solves the I2C multi-hosts - from the control conflict and the communication protocol question, then realized simply, highly effective, the reliable correspondence. 3 examples (double monolithic integrated circuit structure, multi-purpose low power loss systems) (1) hardware W78LE52 and EMC78P458 compose a battery power supply, to be possible the long-distance correspondence industry flowmeter. 78P458 uses the 32.768kHz crystal oscillator, the operating current is low, non-stop run, real-time gathering sensor’s pulse and temperature, pressure and so on some simulation quantity; W78LE52 picks the 11.0592MHz crystal oscillator, because its operating current is big, uses the interrupted work, is responsible for functions and so on current capacity gamma correction, parameter input, liquid crystal display, with superior machine correspondence, its UART uses in the long-distance correspondence. Correspondence connection partial line as shown in Figure 1, 2 monolithic integrated circuits use in common 1 piece of I2C connection FRAM (FM24CL16) composes two main one from the I2C main line control mode, W78LE52 P3.5, P3.2 with 78P458 P51, the P50 connection make handshake holding wire A and B separately. We (the i.e. A line) define handshake line A as the main line control, the indicatrix, mainly uses in gaining the main line domination and the distinction main line whether “busy”; Handshake line B (the i.e. B line) defines as the call-wire, mainly uses in informing opposite party to take the data. (2) I2C bus arbitration What because we use is two hosts one from I2C main line way, therefore prevents 2 main engines simultaneously to operate from machine (against conflict) is a very important question. Has the hardware I2C module component is generally this, the component interior has 1 bus arbitration and the main line overtime timer: After main line overtime timer overtime, instructs the main line to be idle, by now the monolithic integrated circuit might issue the gain main line order, the bus arbitration after a series of operations the confirmation gain main line succeeds or the defeat; The overtime timer reset, the later each SCL change of state carries on the reset to the main line all main engine’s overtime timer, prevents it to overflow, instructed that the main line is being at “busily” the condition, finished until a main engine to the main line control no longer produces the SCL pulse; The overtime timer overflows, the main line returns “idle” the condition. But the present majority monolithic integrated circuit has not provided the hardware I2C module, moreover works as when 2 main engine’s operating frequency differences are big, the overtime timer fixed time value can only suppose for the great value, will like this also affect main line’s use efficiency. Following introduced that one kind (I2C read-write operation procedure’s software simulation very sees with the software simulation I2C bus arbitration’s way, here no longer states): With 1 handshake line A, flow chart as shown in Figure 2, when A line high level, instructed that the main line is idle; When a main engine must gain the main line domination, inquires the main line first to be whether idle, “busy”, then withdraws, the free time, then transmits a test sequence to a line (for example: 1000101011001011), after each time transmits the position “1″ reads A line condition. If the read condition is “0″, withdraws immediately, explained that had other components already to forestall to gain the main line; If a sequence read’s A line condition is correct, then explained already succeeds obtains the main line domination, by must pull the low A line to instruct that main line “busy”, until read-write Gao AXIAN, enables the main line to return to “idle” the condition. The different main engine uses the different test sequence, or has the random test sequence, the test sequence length may choose long somewhat, like this may increase the arbitration the reliability. (3) communication protocol A reliable communication system, besides the good hardware circuit, the communication protocol is also very important. In the monolithic integrated circuit system RAM resources with carry out in the speed very limited situation, a simple and direct effective agreement is very important. Below introduced specifically one kind is quite suitable for the monolithic integrated circuit correspondence agreement, the data transmits by a package of form. Data packet structure: ①Baotou - - instruction data packet’s start, is advantageous to the package of complete examination, sometimes may abbreviate; ②The address - aerodynamic data package must transmit goal address, if only then the correspondence or the hardware discrimination address may abbreviate; ③Packet length - - instruction entire data packet length; ④The order - - instructs this data packet the function; ⑤The parameter - - needs to transmit data and parameter; ⑥The verification - - confirmation data packet’s accuracy, may be and the verification, different or the verification, the CRC verification and so on or is their combination; ⑦Wraps the tail - - instruction data packet the ending, is advantageous in the package of complete examination, sometimes may abbreviate. (4) corresponds the flow First, must divide each region in FRAM, each monolithic integrated circuit’s parameter area, data receive area and so on. Then, the monolithic integrated circuit might to another monolithic integrated circuit transmission data packet, after end of transmission, through transmitted 1 pulse to handshake line B to inform opposite party to take the data; After the receiving end read data and carries on processing, the transmitting end data receive area reads in the feedback data or the correspondence defeat to FRAM in symbolized that transmits 1 pulse response transmitting end again to handshake line B. Table 3 are the monolithic integrated circuit 1 starts 1 time with the monolithic integrated circuit 2 between correspondence example. If needs monolithic integrated circuit 2 transmission, only need exchange the operating process then. Table 3
4 summaries May know through the practice, above method is feasible. Compares with other methods has distributes the merit: ①Simple. Takes the monolithic integrated circuit mouth line few (SCL, SDA, handshake line A, handshake line B). ②General. The software simulation I2C main engine way, may correspond between any type monolithic integrated circuit. ③Highly effective. Because uses the data buffering, may in the different clock rate, between the friction speed monolithic integrated circuit correspond; When read-write data, may the I2C main line’s maximum speed carry on, may realize 1 transmission mass data; When a monolithic integrated circuit to FRAM transmission data, another monolithic integrated circuit does not need 11 to make the response or the waiting, may carry on other procedure operation, raises the software work efficiency. ④Nimble. The correspondence hardware interface regarding each monolithic integrated circuit is coordinated, through the software disposition, each monolithic integrated circuit already may according to need to transmit the correspondence on own initiative, may also only respond other monolithic integrated circuit’s call. ⑤Easy to expand. Through increases the address recognition line, the revision communication protocol, then makes many machine correspondences. The following is the address which needs to pay attention: ①In order to raise the correspondence efficiency, handshake line B should better use the interrupt port, negative pulse width needs certainly to satisfy the speed low monolithic integrated circuit signal of stop request. If does not have interrupt to increase 1 mouth line, with change port condition’s method notice opposite party, waits for opposite party to inquire, but is not negative pulse. ②Transmits negative pulse when to opposite party, should shield own interrupt. ③Because the parameter and the correspondence buffer simultaneously are located in identical piece FRAM, must avoid to the parameter part misoperation. A good solution is deposits the parameter in the address second half of (A2=1), when carries on the communication operations, pulls (address the FRAM WP pin to write protection high in second half of unit), like this may prevent when effectively the examination to parameter area misoperation. ④Because I2C main line in a time section only then 1 main engine and 1 from machine, when therefore 1 monolithic integrated circuit writes the correspondence data, another monolithic integrated circuit cannot to FRAM carry on the operation. If needs real-time, to read in frequently FRAM parameter, please in advance read in the parameter the RAM unit use or other increases deposits specially the parameter the chip. |
this way will be very difficult to simulate from machine the pattern, correspondence both sides needs to make the response to each, correspondence speed and the software resource expenses will form a very big contradiction, will process is not good will cause the system overall performance to drop suddenly. This method can only use in the communication load extremely few situations.
