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Abstract: Introduced the PowerPC series microprocessor exceptionally with the interrupt. Meanwhile as the example realizes the method take MPC555 to the embedded system from ROM and the RAM guidance characteristic and the technology to carry on the comparison, gave MPC555 to realize the method from the RAM fast guidance.
Key word: MPC555; BOOT; Exception vector; Interrupt; Mapping 1 introduction The embedded system is take each kind of embedded microprocessor as the essence computer control system. It was the computer hardware and software’s aggregate 熗 ǔJ smart has inserted to the object system in completes some kind of specific function to design. MPC555 is Motorola MPC500 the PowerPC simplification set of instructions class 32 microprocessors. It can work under - 45℃~125℃ the adverse circumstance, its work clock may reach 40MHz. As a result in product development’s later period, usually needs to record the procedure with the simulator fever to ROM, but the procedure is lower than in the ROM running rate in RAM the running rate. In order to enhance the procedure the running rate, often needs to duplicate on electricity initialization stage the ROM in procedure in RAM, or through dual mappings ROM address mapping exterior RAM. This article take MPC555 as an example, gave has realized specifically from RAM the procedure fast guidance movement the method. 2 PowerPC555 several basic concepts 2.1 exceptionally with interrupt Exceptionally usually is refers to the change normal procedure class and the machine state event. For instance system reset, demultiplier zero crossing, system call instruction, each kind of main line mistake and so on. When an unusual event occurs, usually will have a fast hardware equipment’s transformation or the processor branch to an address (exception vector), and one unusual type will correspond an address in the situation. The interrupt is the unusual one type, usually causes by the external interrupt input pin or the installment interrupt request. In the PowerPC structure, all interrupts share an exception vector displacement, is called “the external interrupt”, usually the mapping offset address is 0×500. 2.2 exception vectors and exceptionally approach the meter After exceptionally occurs, first is distinguished, then machine’s immediate condition is preserved, by now the processor started from some address to carry out, the exception vector is this address. With 68000 structures different (its vector is indicator), the PowerPC vector is the fixed address. Each exceptionally has its exception vector, the exception vector is equal to the base address and sum of the vector displacement quantity. The unusual base address usually is 0×0 or is 0xFFF00000, this is decided by the MSR[IP] position establishment. Table 1 arranges in order is MPC555 exceptionally approaches the meter. And NMI refers to right and wrong shielding property interrupt. Table 1 exceptionally approaches the meter
Table 2 replacement disposition character choice
2.3 replacement disposition character After on electricity or replacement, the microprocessor first reads the replacement disposition character, the replacement disposition character decided by 3 kind of start working pattern: (1) exterior data bus pin DATA 煟 Egyptian sea Chang Bao牐 (2) internal default constant (0×00000000); (3) internal NVM register value (CMFCFIG); Table 2 have given the replacement disposition character choice method. Usually chooses the third kind, namely uses the simulator to read in beforehand the disposition character register CM-FCFIG. And with CMFCFIG in IP position decision procedure entry point address, if IP is equal to 0, then the entry point address is 0×0, if IP is equal to 1, then the entry point address is 0xfff00000. Embedded system’s application procedure is generally is solidified moves in ROM. Usually the available assembly language compilation start-up procedure completes system’s hardware as well as the software movement environment initialization. The start and the application procedure may solidify in ROM 熞 permit the melon to eat admonish are lowly together coil thoroughly the inferior emperor to jump wan the roundworm to skip far to the replacement exception vector entry point address place start the executive routine. In the source document translation link production’s object file, the code, the data place in the different section. But in object file’s .data Duan Zeyi system RAM is the reference address, therefore in system initiation time needs in copy ROM .data to arrive at RAM, completes RAM the initialization. 3 realize the method from the RAM fast guidance movement 3.1 dual mapping If the procedure is burnt records to microprocessor’s internal ROM, may through the MPC555 unique function - - dual mapping internal FLASH address mapping exterior RAM, realize the fast guidance movement. When enables the dual mapping functions, the internal FLASH area correspondence’s address does not have an effect, but maps the exterior RAM area address has an effect. When concrete operations, first records the procedure fever to internal FLASH, then when on electricity the procedure from the internal FLASH copy to exterior RAM, enables microprocessor’s dual mapping function again finally. Thus, the procedure might move in exterior RAM. Shown in Figure 1 is its flow chart. The concrete procedure code is as follows: INT Vectors /* system reset */ .skip 0×0100 煟 INT Vectors start #/* establishes RAM and ROM memory block */ #/*OR2=0xFFF00000 selects patches or strips of land as worth saving for seed RAM size 1M*/ lis r5 0xfff0 ori r5 r5 0×0000 lis r4 OR2@ha stw r5 OR2@l 煟 Ying Chu #/* BR2=0×0400003 RAM base address 0X400000 32 mouth size */ lis r5 0×40 ori r5 r5 0×0003 lis r4 BR2@ha stw r5 BR2@l 煟 Ying Chu #/* copy interior Flash to exterior RAM */ li r6 煟 Egypt 0 lis r4 煟 Egypt 40 ori r4 煟 Ying Chu 煟ai 0000 lis r5 煟 Egyptian fff0 ori r5 煟 Ying Dan煟 Egypt 0 loop 1 lhzx r7 煟 Ying Ding煟 Ying sthx r7 煟 Ying Ding煟 Ying addi r6 煟 Ying Ding煟 Egypt 2 li r8 煟 Egyptian b00 cmp r6 煟 Ying bne loop 1 #/* causes CS2 to select patches or strips of land as worth saving for seed area invalid */ #/* BR2=0×0400003 basic register 2 */ lis r5 0xfff0 ori r5 r5 0×0000 lis r4 BR2@ha stw r5 BR2@l 煟 Ying Chu # the/* dual mappings enable */ #/* DMOR=0xFFF00000 selects patches or strips of land as worth saving for seed the dual mapping areas Size 256k */ lis r5 0×7000 ori r5 r5 0×0000 lis r4 OR2@ha stw r5 OR2@l 煟 Ying Chu #/* DMBR=0×0400003 dual mapping area base address 0X0 32 mouth size */ lis r5 0×0 ori r5 r5 0×0005 lis r4 BR2@ha stw r5 BR2@l 煟 Ying Chu ba INT Initialize … 3.2 duplication law Regarding with chips and so on MPC500 homologous series MPC561 and MPC562, because the microprocessor interior does not have ROM, must therefore outside expand ROM. In this case, may record the procedure fever to exterior ROM, then when on electricity again procedure from the exterior ROM copy to exterior RAM, thus enables the procedure to move in exterior RAM. As example flow chart as shown in Figure 2 take MPC555. In this method, the procedure only before redeploying the memory block to move in exterior ROM, but after redeploying the memory block moves in exterior RAM, therefore raised the procedure running rate. This method during the operation, first records the procedure with the simulator fever to exterior FALSH, the entry point address is 0xfff00000, then off-line movement. In this example, exterior FLASH is 16 main lines, exterior RAM is 32 main lines. Below as the example gives the concrete program code take MPC555. INT Vectors /* system reset */ .skip 0×0100- 煟 - INT Vectors start #/* establishes RAM and ROM memory block */ #/*OR2=0xFFF00000 selects patches or strips of land as worth saving for seed RAM size 1M*/ lis r5 0xfff0 ori r5 r5 0×0000 lis r4 OR2@ha stw r5 OR2@l 煟 Ying Chu #/* BR2=0×0400003 RAM base address 0X400000 32 mouth size */ lis r5 0×40 ori r5 r5 0×0003 lis r4 BR2@ha stw r5 BR2@l 煟 Ying Chu #/*OR0=0Xfff80000 selects patches or strips of land as worth saving for seed FLASH size 512k*/ lis r5 0xfff8 ori r5 r5 0×0000 lis r4 OR2@ha stw r5 OR2@l 煟 Ying Chu #/* BR0=0xfff00803 RAM base address 0Xfff00000 16 mouth size */ lis r5 0xfff0 ori r5 r5 0×0803 lis r4 BR2@ha stw r5 BR2@l 煟 Ying Chu #/* copy exterior Flash to exterior RAM */ li r6 煟 Egypt 0 lis r4 煟 Egypt 40 ori r4 煟 Ying Chu 煟ai 0000 lis r5 煟 Egyptian fff0 ori r5 煟 Ying Dan煟 Egypt 0 loop 1 lhzx r7 煟 Ying Ding煟 Ying sthx r7 煟 Ying Ding煟 Ying addi r6 煟 Ying Ding煟 Egypt 2 li r8 煟 Egyptian b00 cmp r6 煟 Ying bne loop_1 #/* redistributes memory block */ #/* BR0=0×600803 */ lis r5 0×60 ori r5 r5 0×0803 lis r4 BR0@ha stw r5 BR0@l 煟 Ying Chu #/* OR0=0xFFf80000 selects patches or strips of land as worth saving for seed flash 512k cyclical */and so on 1 clock lis r5 0xfff8 ori r5 r5 0×0003 lis r4 OR0@ha stw r5 OR0@l 煟 Ying Chu #/* OR2=0xFFF00000 selects patches or strips of land as worth saving for seed RAM 1M */ lis r5 0xfff0 ori r5 r5 0×0000 lis r4 OR2@ha stw r5 OR2@l 煟 Ying Chu #/* BR2=0xfff00003 base address 0Xfff00000 32 mouth size */ lis r5 0xfff0 ori r5 r5 0×0003 lis r4 BR2@ha stw r5 BR2@l 煟 Ying Chu ba INT_Initialize … 4 concluding remark Author take MPC555 which introduced to the article in as example 煻 source cherry remote grain of Tu Menxi leads the movement two kinds to realize the method to carry on the test contrast. The result proved: The procedure compared to enhanced more than 1 time in the RAM running rate in FLASH, thus the program run speed had the very big enhancement. |
MPC555 has the formidable floating-point computation handling ability and supports the complex algorithm. This component has many independent communications and the time processing module, the interior has 448k byte flash, therefore, this product, even if in individual hand, may also momentarily renew the promotion. MPC555 has at the same time industrial standard JTAG and the BDM connection, thus causes the product hardware and software’s debugging and the experiment is more convenient quickly. MPC555 already in professions and so on aerospace, automobile manufacture, relay protection obtained the widespread application.
