Abstract: PCI9052 is one kind of PCI main line subordinate connection chip which PLX Corporation promotes (does not have the DMA function). It has provided the convenient local main line and the PCI main line’s connection, avoids the user facing the complex PCI main line agreement directly. GP2010 is the General Electric Plessey semiconductor organization for the global positioning system (GPS) the receiver design second generation of radio frequency high frequency end component. It GPS radio-frequency signal under frequency conversion after 4.309MHz intermediate frequency (IF) carries on 5.714MHz 2bit (A/D) the quantification. In the article mainly introduced how realizes the GPS signal quantification memory using PCI9052 and GP2010.
Key word: PCI main line GPS DMA
Introduction
Global positioning system GPS (Global Position System), may provide the real-time localization, the speed and the time information to the user. Present’s GPS receiver mostly uses the hardware circuit to carry on the code related operation, the structure is complex, the renewal promotes is quite difficult; But the GPS receiver are been few based on the software radio the electric circuit limit, the renewal only need adjust the corresponding software, is very nimble. This data acquisition card is considers the design based on above.
1 PCI9052 characteristic and function
PCI9052 (hereafter refers to as 9052) provides the high performance to meet the oral plate card and the PCI main line’s connection from goal PCI, supports the wide scope speed the local main line, highest may reach 132 
MB/s the transmission speeds. May realize multiplying/non-multiplying 8, 16, 32 local bus interfaces to 9052 programming. 9052 also have internal FIFO to be possible to accelerate the local main line’s operation, in addition it also has the following function:
①Supports PCI the r2.1 edition, may the ISA card transformation be the PCI card conveniently;
②The support from the goal mode of transmission, may carry on to the memory space arises suddenly reads/writes, to I/O space single reference;
③2 local interrupt bus disposition;
④Programmable local main line disposition;
⑤Serial E2PROM disposition;
⑥4 this locality select patches or strips of land as worth saving for seed the pin, 5 local spaces;
⑦Many kinds of local reads/writes the operator schema, realizes PCI and the local connection conveniently.
Figure 1 has given 9052 internal structures.
Front end 2 GP2010 radio frequencies component
GP2010 (hereafter refers to as 2010) is front end the GPS receiver design radio frequency the component, it receives GPS (L1) the modulation signal. L1 is 50 /Hz information code speeds after the 1.023MHz pseudo-random code wide frequency by the BPSK way modulation the wide frequency signal which forms in the 1575.42MHz carrier. The signal level before entering the antenna probably only then - 130dB, the band width is 2.046MHz, therefore L1 basically is covered by the noise. 2010 produce 1.4GHz, 140MHz, after the internal phase-locked loop frequency synthesizer to carry on the mixing separately with the 31.11MHz third-level clock with the radio frequency input L1 signal, also passes through outside 3 level of filter stop bands to disturb, finally transforms it to the 4.309MHz intermediate frequency, then carries on 5.714MHz the sampling to realize a/D transformation (2 quantifications, sign bit SIGN and data position MAG). Must be higher than two time of signal band widths according to the Naikuisite law to the bandpass signal to carry on the sampling only then to be possible the non-distorted restoration, must consider with the 5.714MHz speed sampling in the signal spreading process the Doppler effect which produces as a result of the relative motion causes the signal band width broaden the reason. Quantized data in each clock’s rise along output. Figure 2 gives 2010 internal structure drawings.
Figure 2 GP2010 interior structure drawing
3 data acquisition card system structure
The GPS signal data acquisition card realizes a basic group GPS satellite signal gathering work. Because 2010 are 2, the 5.714MHz sampling speeds, we first carry on FPGA 2 bit data the string and transform, after causing its each full 32, carry on a transmission to save, like this saves the speed to become 357.12kHz. The buffer selects 4 18k×16 positions FIFO, like this may abbreviate the address to have logic. In the programming, the sampled data first stores FIFO (A), treats Man Hou will have the corresponding interrupt, the interrupt service will read data. In reads in the process, the sampled data will continue to read in FIFO (B), may input so repeatedly the data the computer memory. When selects the buffer, suggested that in the feasible situation, the capacity is bigger is better. Because on the PCI main line, is applying besides the design gathering card to take the main line unceasingly, will also have other equipment to take, if the buffer insufficient senior general will lose the sampled data. The FPGA major function is realizes the data serial transformation, the control sampling process and with the FIFO interface logic. Figure 3 is this data acquisition card system diagram.
in 4 9052 uses should pay attention question
9052 internal disposition registers are through exterior serial E2PROM on the electricity load. 9052 will act according to this E2PROM the condition to decide its internal register’s value automatically. If E2PROM does not have (this time E2PROM and 9052 connection data pin should add on pulls resistance) or its interior does not have the effective value, 9052 its internal register disposition will be the default values. What is worth mentioning, when the E2PROM interior has not burnt writes for the effective value, should guarantee that it starts 48 for entire “1″; , on system electricity possibly will make the mistake.
9052 have 5 local spaces, the user may carry on the corresponding disposition according to the actual need. When disposes the local space I/O, reads to this space/writes the operation only to be able single to carry on. Develops (the API function which using PLXMon the driver transfers it to provide) to carry on I/O to read/writes, the speed will be very slow (will not surpass 500kHz generally); But like disposes the memory space, the user will have many kinds of turning on patterns, may raise the turning on speed greatly.
Arises suddenly the pattern is to raise the local main line operating speed to design. In this pattern period, 9052 provide a transmission to start with the stop signal. After starting the signal effectively, the address (highest might reach 40MHz) by the local clock’s frequency to increase progressively, may using the Bterm# pin whether effective to terminate arises suddenly the operation. Because FIFO only needs a mouth address, in design to use its fast memory visit (to arise suddenly visit) the characteristic, we have assigned the 36KB address space for it, guaranteed that FIFO selects patches or strips of land as worth saving for seed in this scope is effective throughout. Figure 4 is one time arises suddenly reads the succession. And LCLK is the local clock, ADS expressed effectively a time transmits the start, BLAST expresses this transmission termination effectively.
Must clarify a concept in this: The Pentium series computer (points to CPU), does not support arises suddenly reads the operation, only possibly produces single reads the operation. If the user wants to realize on the PCI main line arises suddenly the operation (the FRAME signal to be effective, unnecessary PCI clock cycle), should use supports the DMA transmission the chip, like PLX9054. But 9052 single will read the PCI main line on the operation to transform many times arises suddenly for the local space in the operation.
5 PLXMon and PLX component driver development
PLXMon is PLX Corporation specially for its product development testing software. Inserts the PCI trough in user’s board card, after and has installed the driver which PLXMon provides, starts this software to be possible to observe and to revise the chip interior register’s value, and may carry on the test to the memory space.
Under Windows driver including hardware physical equipment’s driver and filing system and so on non-physical equipment’s hypothesized device driver, what we compile is the hardware physical equipment’s driver. Windows kind of operating system (Windows 95, Windows 98, WindowsNT, Windows 2000) to guarantee that its security, the stability and the probability, limit visit to the application procedure hardware source, the user need has the detailed understanding to the system hardware and the operating system software to be only then potential the highly effective driver, therefore the development cycle is long. Development software which provides using the third party, may reduce the development time greatly, but efficiency not necessarily high, especially appears somewhat incapable to the timely request strict procedure.
①Device Developer Kit(DDK). In this software included the related equipment to actuate the head document which and the storehouse document, the debugging aids and the procedure model the development the documents, the translation needed; But because DDK is mainly uses the assembly language to carry on the description, develops is quite difficult.
②VtoolsD. This software package is based on C/C , supports BorlandC and VisualC , uses and maintains is quite convenient.
③WinDriver. The permission user uses Visual C , Borland or other Win32 programming tool software (UserMode) on compiles the device driver in the user pattern.
④PLXMon. PLX Corporation specially the driver development package which and the testing software provides for its chip, similarly may compile in the user pattern. Supports Visual the C environment.
Figure 4 arises suddenly reads the succession
When develops the procedure, we discovered that PLXMon and WinDriver are incompatible, moreover, only if has official edition WinDriver; Otherwise the probation period from now on, will use the driver which it develops to be unable to use. Therefore the establishment uses PLXMon, only need including the corresponding head document, the user then be possible to transfer the API function which conveniently it provides, in the gauge block card resources carries on the visit. The basic inquiry which the following procedure fragment is when debugs circuit wafer compiles to interrupt whether effective to read the buffer. Transfers the function is the API function which PLXMon provides. And: PlxPciBaseAddressesGet () is obtains in the board card the storage space physical address, but * (Data i) =* (U32*) (va. Va3) is loads this spatial value the computer memory.
Figure 5 is the driver flow chart.
The segment is as follows:
Example:
rc_w=PlxPciBaseAddressesGet(hDevice,&va);
while(TRUE) {
Int_Flag=*(U32*) (va. Va0 0×4c);
if(Int_Flag[0]&4) {
for (i=0; i<FIFO_Size; i )
* (Sample_Data i)=*(U32*) (va. Va3);
* (U32*) (va. Va0 0×4c) =Clear_Flag;
break;
}
}
Conclusion
As a result of the PCI main line’s high-speed characteristic, causes it widely to apply in the high speed data gathering system, has solved real-time problems effectively and so on gathering, live transmission and real-time memory. But the PCI bus control unit special-purpose chip’s appearance reduced the PCI bus hardware equipment’s development cycle, caused the hardware equipment’s reliability and the stability had the big enhancement. In opens in the process, we discovered that if wants to have the high efficiency operating characteristic, the use third party provides the driver development package is not too always ideal, especially regarding high speed sampling and real-time strict system. The user must conform to the driver which using the DDK development oneself request. This data acquisition card has realized a group GPS signal gathering work, will carry on the digital signal for next use general PC machine the capture, the track and the demodulation, will realize the software radio GPS receiver to build the foundation initially.
