Key word: High speed data gathering; High speed buffer; Magnanimous buffer; DSP; FPGA
1 introduction
The high speed data gathering system present in the radar, the sound navigation and ranging, the software radio, domains and so on transient signal test obtained the widespread application. Its key technologies is the high speed ADC technology, the data storage and the transmission technology and the antijamming technology. This article in analyzed in the high speed multichannel data acquisition system to save subsystem’s performance requirement and in the design proposal foundation, proposed the high speed buffer and the magnanimous buffer plan, and applied successfully this plan in DSP multichannel supersonic signal gathering and the processing system.
Performance requirement which saves to the high speed multichannel sampled data: First, high speed, in high speed data gathering uses now ADC has achieved several dozens even several hundred MSPS the levels, this request sampled data memory’s speed must with it match, also uses the high speed buffer; Second, large capacity, its reason is multichannel high speed data gathering can have the huge data stream. 4 channel 40MHz sampling rate 16 accuracy data gathering board parallel sampling 0.1s will have the 32MB data quantity, therefore, usually the need magnanimous buffer saves the sampled data.
2 high speed buffer realizations
Usually the constitution high speed buffer’s plan has three kinds:
The first kind is FIFO (advanced leaves the way first). The FIFO memory looks like the data pipeline to be the same, the data from a pipeline’s inflow, flows out from another, enters advanced the data flows out first. FIFO has two sets of data lines not to have the address wire, may write the operation in its end, but reads the operation in another end, data in smooth migration, can thus achieve the very high transmission speed and the efficiency, and as a result of has omitted the address wire but is advantageous to the PCB board wiring. The shortcoming is can only the smooth read-write data, thus appears quite stereotypical, moreover large capacity high speed FIFO is expensive;
The second kind is the pair of mouth RAM way. Double mouth RAM has two sets of independent data, the address and the control bus, thus may from two ports at the same time the read-write, but does not disturb mutually, and may the sampled data from a port read, but reads out by DSP from another port. Double mouth RAM can also achieve the very high transmission speed, and has the random access merit, the shortcoming is large capacity high speed pair of mouth RAM is very rare, and the price is expensive;
The third kind is the high speed SRAM cut way. High speed SRAM only then a set of data, the address and the control bus, may receive on separately a/D switch and DSP through the three states of matter cushion gate. When A/D sampling, SRAM cuts A/D switch one side from the three states of matter gate, causes the sampled data to read in which. After a/D sampling had ended, SRAM cuts DSP one side again from the three states of matter gate, so that DSP can carry on the read-write. This way’s merit is SRAM may the random access, simultaneously large capacity high speed SRAM easy to obtain, and the moderate cost, the shortcoming is the hand-off control electric circuit is quite complex, and can only by a/D switch and the DSP time sharing read-write.
After the overall evaluation above three high speed buffer plan’s performance, the price and realize the conveniences, the author selects the third kind of plan (i.e. high speed SRAM cut way) to constitute a/D sampling high speed buffer. System’s sampling and memory part’s functional block diagram as shown in Figure 1.
In Figure 1, SRAM selects IS61LV25616-10T, the capacity for 256k×16bit, the access speed is 10ns, uses two pieces then constitute 256k×32bit high speed buffer. When a round sampling starts, DSP sends out the trigger pip to give CPLD, the latter after 50MHz crystal oscillator clock two frequency divisions obtains the 25MHz sampling clock to provide to 4 group A/D switch AD9225, simultaneously carries on 25MHz, the 12bit A/D transformation to 4 groups supersonic signals. The transformation result divides into two completely same data channels to carry on processing, each data channel processes two group A/D transformation result, each data channel contains piece of FPGA (the scene programmable gate array), piece of SRAM and after that electric circuits and so on data three states of matter gate. FPGA may receive two group A/D transformation result and carry on the multiplying in its interior, by turns it group 50MHz, the 12bit data stream to send in the IS61LV25616 buffer. FPGA completes the data channel multiplying principle as shown in Figure 2.
FPGA selects EP1K50, its logical gate number is 50,000, contains 10 EAB (inserting array block). Each EAB in fact is 4kbit RAM, may use for to construct FIFO, pair of mouth RAM and so on. This system applied two EAB to constitute two 256×16bit FIFO, thus might send in separately two group A/D transformation result two FIFO, then read out alternately in the FPGA out-port’s two FIFO in data reads in IS61LV25616, each FIFO each time read out 128 sampled data. A/D switch’s output is 12 bit data, but outside FPGA internal FIFO and the piece the IS61LV25616 data word width is 16. When memory, transmission, will be high 4 to make up 0 then. Two group A/D sampling speed is 25MHz, after the multiplying, outputs the speed is 50MHz, this speed is definitely may achieve regarding IS61LV25616 and EP1K50. The FPGA function besides constructs FIFO to realize the data channel multiplying, but may also take cooperates the processor the DSP control to carry on some simple highly effective data pretreatment by the board on (for example interpolation, to average, the FIR filter and so on). Simultaneously may use EDA tool MAX PLUSⅡ10.0 carry on the design, the translation and the simulation to the EP1K50 logical algorithm, then downloads to EP1K50 in realizes the predetermined function.
Besides FPGA, the system also used piece of CPLD (complex programmable logical component) to control the sampling. The former mainly uses in the data channel carrying on the cushion multiplying as well as the pretreatment to a/D sampling result, the latter is responsible to produce a/D sampling clock as well as to produce the address as the address counter and provides to two piece of IS61LV25616 in order to store a/D sampling result and so on. CPLD does not look like FPGA such to be able to complete the complex logical function and the signal processing algorithm, but it has a higher speed, and has the fixed consistent latency the base pin to the base pin, thus in design debugging time easy to obtain the simple reliable relations fixed time, is suitable for to realize the high speed counter, the trigger, the decoder and so on fixed time to request the quite strict situation. This system uses MAX7128AE to control the sampling, its achievable function as shown in Figure 3.
MAX7128AE may use in realizing two 18 bit address counter, it has the address bus switch cut function, in A/D sampling period can carry on the address counting by 25 MHz frequencies by to take the high speed buffer the address wire. After a round A/D sampling had ended, the system may cut the high speed buffer address bus DSP the address bus, then reads in the high speed buffer by DSP a/D transformation result and carries on processing. The high speed buffer IS61LV25616 data bus company arrives at FPGA at the same time in order to sampling period accept the multiplying a/D transformation result; On the one hand arrives at DSP through the three states of matter gate company the data bus, so that after the sampling had been able to have ended reads the sampled data by DSP.
3 magnanimous buffer’s designs realize
This system used two piece of 256k×16bit capacity SRAM to take the high speed buffer, in system’s 4 channels may simultaneously save each channel 128k sampled data. Under the 25MHz sampling frequency, a time may gather saves the 5ms many profile data. Regarding the supersonic signal’s single launch/receive, this kind of sampling time length had been already enough, but was quite difficult regarding many raid of sampled data’s memory. If through the PCI main line, the USB connection and so on fast communication way passes to the sampled data the main engine to carry on processing or stores the hard disk, should satisfy the giant main line band width which the live transmission sampled data needs. Take 25MHz, the 12bit sampling precision as an example, at the same time 4 channels the sampling will have the 150MB/s data stream, this with difficulty achieves regarding any main line. Solution is uses DSP on the data acquisition board to carry on the pretreatment to the gathering data, after causes processing the data quantity big reduction, then uploads again for the main engine reduces the main line transmission pressure and the main engine processing burden, thus avoids the data communication bottleneck. This kind the DSP execution computation intensity duty and carries on the dispatch management by the board on by the superior main engine the distributional processing mechanism to be possible widely to use in many high speed data gathering and the processing system. But DSP provides the large capacity memory for the board on to take its procedure and the data-carrier storage is very essential. Considered this system uses DSP the unique feature and the large capacity sampled data memory need, the author selects SDRAM to take the board Shanghai quantity memory.
In system’s DSP is Analog Devices Corporation’s ADSP-21065L, this is section of performance-to-price ratio very high 32 floating point DSP. Its peak value floating point calculation speed is 180M FLOPS, internal has 68kB RAM, may use in the procedure or the data memory, outside the piece the data bus is 32, outside the piece the address bus is 24, has 4 to select patches or strips of land as worth saving for seed the signal output, each selects patches or strips of land as worth saving for seed the signal the addressing space to be possible to reach 64MB, moreover, it also has many high speed synchronized serial ports as well as the formidable DMA function. But the most characterful spot was its interior integrated a SDRAM controller, therefore could direct drive exterior SDRAM. Usually the SDRAM control is quite complex, needs according to the succession to stipulate that actuates its line, the row to choose the line of flux and time sharing provides line, the row address, in addition must fixed time refurbishing. Generally is by the special SDRAM controller to its operation, or uses FP-GA to design the SDRAM controller, but this can increase system’s order of complexity. But ADSP-21065L can the direct drive and controls outside the movie-making SDRAM, when use, so long as establishes the good related register in the procedure, then starts SDRAM with an instruction on electricity succession then. Hereafter the procedure to SDRAM the accessing operation is transparent, may visit outside the ordinary piece SRAM to visit it equally likely, therefore is convenient, therefore may use large capacity (may reach 64MB) the high speed inexpensive SDRAM chip to take ADSP-21065L the magnanimous piece external memory. This system uses two piece of 4M×16bit SDRAM chip HY57V641620 to constitute the 16MB magnanimous buffer (to see also Figure 1). Thus, 16MB storage capacity, if uses for to redeposit sampled data, may save a 2M data which 4 channels simultaneously gather, may achieve 0.08s under the 25MHz sampling rate the total recorded time, this speaking of this system was already enough. Moreover through selects the larger capacity SDRAM chip also to be possible to expand conveniently the magnanimous buffer capacity to 32MB, 64MB.
To a/D sampled data pass along the magnanimous buffer many times from the high speed buffer, if lets ADSP-21065L in the high speed buffer read the sampled data with the instruction way from the piece, then reads in the piece open sea quantity buffer, will take ADSP massively the running time, moreover the transmission speed will be also slow. Therefore, the author uses ADSP the DMA function to carry on the transmission. ADSP-21065L has many DMA channels (includes two exterior DMA channels), thus may carry on the high speed data transmission. Its exterior DMA channel may complete between the external memory and the peripheral device DMA transmission originally, but if one of the two is SDRAM is not good. Therefore, time actual use generally relays through ADSP-21065L internal RAM, then completes the high speed buffer again to the magnanimous buffer data transmission, concrete procedure as shown in Figure 4.
The ADSP internal start has 1k×32bit exterior the RAM block constitution relay area, may use the DMA channel 0 to carry on a/D high speed buffer to the internal RAM DMA transmission, exterior simultaneously uses the DMA channel 1 to carry on the internal RAM area to the magnanimous buffer SDRAM DMA transmission. Under the 60MHz ADSP basic frequency, the former’s DMA transmission speed may reach 120MB/s, the latter’s DMA transmission speed may reach 240MB/s. After exterior the DMA channel 0 complete a transmission, exterior the system will start DMA the channel 1 DMA transmission; After but when the latter’s DMA transmission completes, 熛 low chen starts the former’s DMA transmission once more. Continue the circulation like this, sampled data pours into up to the SDRAM magnanimous buffer until A/D in the high speed buffer’s 1MB, this process probably needs 13.1ms.
4 conclusions and improvement
Through several kind of A/D sampling high speed buffer realizes the plan to the high speed data gathering system to carry on the contrastive analysis, unifies this system’s unique feature and the performance requirement, uses SRAM to take the gathering system which a/D high speed buffer constitutes to have the speed to be high, the capacity is big, the control is convenient, price suitable medium merit. Selects high speed, large capacity, low price SDRAM to take the magnanimous buffer to be possible through its exterior DMA channel’s to pour into high speed buffer in sampled data the magnanimous buffer. This kind of design causes system’s A/D sampling memory to have both high speed and the magnanimous merit, simultaneously has the very high performance price ratio. But its remaining deficiency is: ADSP and a/D switch has affected system’s timeliness to a certain extent through the cut main line way time sharing visit high speed buffer. May introduce the plan which as the corrective measure the catarmaran saves visits alternately, namely increases two piece of IS61LV25616 to make group of high speed buffers again by and the existing two piece of IS61LV25616 constitution catarmaran memory block. Because in this way’s ADSP and a/D switch visits these two groups of buffers alternately by the pingpong way, therefore, ADSP and a/D switch can the multi-tasking not need to wait for mutually, thus enhances system’s timeliness.
