Abstract: Gave has used similar DMA the design mentality as well as use pair of mouth RAM, the fast logic circuit and CPU(AT89C51) composition digital profile memory system’s integrated circuit, thus has solved profile data fast gathering and the output demonstration question.
Key word: DMA; Twin port; RAM; Memory; AT89C51 GAL
Along with the signal processing technology’s development, the profile memory becomes day by day important, each type’s profile memory unit are also getting more and more. Is opposite in other profile memory unit, the design most major characteristic which this article gives is the speed is quick, may carry on DMA to save, and does not take the CPU time to come to the signal to carry on processing.
1 system’s system design
Because this design has used pair of mouth RAM and the DMA thought that moreover data gathering, memory and output by logic circuit control, therefore, raised the data oscilloscope’s sampling speed, simultaneously realizes “the real time display” easy, and may when “false” the real-time processing carries on the operation to the data. In addition, the data real time display and “false” the real-time processing may adopt “the DMA permission” to control, its overall project design as shown in Figure 1.
1.1 input circuits
This design’s input circuit is an adjustable gain electric circuit actually, mainly completes to the signal enlargement. This design establishment has 0.01/div, 0.1/div and the 1/div third gear vertical sensitivity, may carry on 1 time, 10 separately to the input signal times and 100 time of enlargements. May use following two kind of plans specifically:
(1) uses the programmable gain to transport puts realizes 1, 10, 100 enlargement factor. Because uses the integration to transport puts, thus the precision is high, the debugging is convenient, but the construction cost is also high.
(2) uses the third-level enlargement, the first level is the follower way, the latter two level of enlargement factor is 10, after each first-level enlargement, some output tap. Concrete connection as shown in Figure 2.
1.2 A/D switch’s choice (1)
A/D switch is the key component which the profile saves. It has decided oscilloscope’s maximum sampling speed as well as the resolution. At present the commonly used A/D switch’s output form has parallel and the serial two kinds, its conversion mode has approaches ADC, integral ADC gradually, ∑-Δ ADC and running water linear ADC.
To this design, should choose high speed A/D obviously. The overall evaluation various aspects’ factor, the author has selected 8 CMOS, the 20MSPS analog-to-digital converter (ADC) TLC5510.
If needs to further enhance the storage oscilloscope input signal the frequency, may consider parallel A/D, namely carries on the time sharing sampling with two piece of A/D to a group signal, because may like this, will not enhance in the component frequency characteristic foundation the input signal band width to enhance one time. Ex analogia, but parallel many A/D enables the input signal the band width to further have the enhancement (in this design not to involve this item, as soon as has interest reader might as well to try).
1.3 memory’s choices
The author has selected two piece of pair of mouth 4kB RAM IDT7134 in this design (4kB). It when two-circuit use, a group corresponds a memory. Use pair of mouth RAM is advantageous to the profile carries on the real-time processing and “false” the real-time processing.
1.4 triggering circuit’s design
Triggering circuit when design has three kind of plans; first, uses the adjustable resistance. Because this input signal occupies in a continual scope, namely the triggering level may change continuously, therefore uses the adjustable resistance to be able the simplified circuit. Second, selects the digital potentiometer to replace the simulation resistance. Although this plan may realize the programmed control, but the triggering level cannot continuously adjustable, and will increase system’s control duty. Third, is composed the triggering circuit by the D/A switch, as shown in Figure 3. In this electric circuit, the triggering level and the Di input’s relations are:
V=VREF Di/2n
In the formula, n is the D/A figure, VREF is the voltage reference.
Can satisfy the triggering level adjustable request using the D/A triggering circuit, but will increase system’s order of complexity. Therefore, should the overall evaluation above three plans.
1.5 GAL and control circuits
a. GAL component
The GAL 煟 spinach 犉 ku usually uses the E2CMOS craft manufacture, the E2CMOS craft characteristic is may the experimental, the low power loss, high speed and may scratch immediately writes. At present the most commonly used GAL component has GAL16V8 and the GAL20V8 two kind of series, they most have 8 out-ports (also programmable input), has 16 and 20 input ends separately.
The GAL component’s characteristic is as follows:
* the convenience programming, the programming unit and the logical disposition may duplicate carries on the programming;
* the high performance E2CMOS craft causes component’s power loss to be very low (biggest movement power loss is 45mA), the speed high (access speed is 15~25ns); The output logic great unit’s disposition enables the design to have a bigger flexibility;
* has the security unit, may carry on the encryption to the procedure to protect the intellectual property rights.
In addition, the GAL component also has output register or’s pre-load function as well as the fixed protection, the input block and adds technical characteristics and the function and so on electricity replacement.
The author selects GAL16V8 to complete the logical function which shown in Figure 4. Its GAL input/output port’s logical relation is:
(abel language)
Aout=(A0#A1#A2#A3);
Bout=! (B0#B1);
Cout1=! (C1);
Cout0= (C0&! S0#! C1&S0#! C2&S0);
In the system numerical part’s logical relation may realize by GAL, not only like this may enable the electric circuit to obtain the simplification, simultaneously may also enhance system’s reliability.
b. Numerical control electric circuit
Shown in Figure 5 is in this system the numerical control electric circuit’s work schematic diagram. When system work in real time display pattern, CPU first carries on the replacement to all control circuit, and makes the address counting to start, then completes A/D in each clock the data output, to read in RAM and the D/A direct output. After the address overflow (full screen demonstrated needs data quantity), will write the RAM address counting signal to forbid again, simultaneously gave the CPU memory to finish the signal.
When the system carries on the profile lock saves, A/D will stop working, and the data quantity which needs the full screen saves in RAM, hereafter the counter only need give the address, then by D/A output wave shape.
When carries on the profile migration, if in the lock saves the single mode in the foundation a screen demonstration to be undecided, that CPU will count N to the address initialization (or - N), and after the output wave shape the new pre-placed number will send in the address mouth line, this time’s CPU may establish the next time demonstration again the first address, will like this then realize profile about to move, will thus demonstrate the profile the random part.
2 system software design cycle
This profile memory system’s master routine divides into the initialization and the keyboard manages two parts. Figure 6 is its master routine diagram. And the initialization module is mainly after the system adds the electricity 熗 is the bu what reason テ machine system the periphery part’s initialization 熑 duo abundant school cherry punishes Bolivia to guarantee the hypothesis which, to the timer and the DMA system original state hypothesis as well as for the system variable evaluation the hook jia armor punctures and so on.
8 pressed key keyboard administration module which are composed of 74LS148 and 74LS76 selects the inquiry method by AT89C51 to carry on processing. In order to enhance system’s reliability, here has not used the interrupt mode. The keyboard manages the function is changes over to the corresponding condition according to pressed key’s function number and the current condition, and carries out the related functional module, then enters the next circulation. In order to facilitate keyboard’s management, this design opened a 8 byte RAM area each time processed when (like this) the keyboard service routine as keyboard’s management control area only to specially visit this area then.
3 reliability designs
In order to enhance this system’s reliability, this design has also used the following several measures:
(1) uses the monitoring circuit. Carries on the monitoring to the monolithic integrated circuit system. Author when design, what uses is the MAX813 micro processing monitoring chip, may enable the procedure through this chip when enters the endless loop to reposition, thus has guaranteed the software system movement reliability, simultaneously, when the system software designs, the author has also used the software watch-dog technology.
(2) in reliable aspect. When system initialization, also has carried on the corresponding establishment with the monolithic integrated circuit to all ports according to various submodules request.
(after 3) system opening, the memory will first move the self-check program, will inspect the memory cell. If discovered that has the continual 9 memory cell to be bad, demonstrates “- error-” on the nixietube, otherwise demonstrates “success”.
