Abstract: FM3808 is the new ultra low power loss non-volatile poss ferroelectric random access memory which Ramtrom Corporation produces, this component may support to the memory block high speed read-write, and may carry on approaches the non-time limit read-. The FM3808 interior besides had the 256kB memory array also to integrate the real-time clock and the system monitoring module, thus the function was very formidable. In the article introduced the FM3808 performance characteristic, the internal structure and the principle of work, have analyzed the TMS320VC5402 DSP parallel guidance loading pattern. Has given DSP and the FM3808 composition parallel guidance connection plan.
Key word: Poss ferroelectric random access memory digital signal processor parallel guidance loading pattern FM3808
1 introduction
The poss ferroelectric random access memory (FRAM) is a section of power failure nonvolatile storage which Ramtron Corporation recent years promoted, its core technologies was the ferroelectricity crystal material. This exotic material’s utilization enables the poss ferroelectric random access memory to be possible simultaneously to have the random packing memory (RAM) and the non-volatile memory’s comprehensive characteristic. Compares with EEPROM, FRAM may the main line speed write data, and after read-in does not need any time delay waiting. The surface EEPROM idling speed and the big electric current read in cause its need with to be higher than FRAM2500 time of energy to read in each byte. At the same time, FRAM has approaches the non-time limit to read in the life, moreover the price does not volatilize lithium electricity SRAM lowly compared to the same capacity many, therefore, FRAM especially qualify these to data acquisition, write time request very high situation. Since FRAM has been published, has relied on its each kind of merit widely to apply in systems and so on survey and medical measuring appliance, aerospace, entrance guard system and automobile flight recorder.
2 principal characteristics have the internal structure
FM3808 is a section of storage capacity for 32k×8bits new FRAM (reduces 16 bytes), it has high speed characteristics and so on read-write, ultra low power loss and non-time limit read-write. Its main feature is as follows:
* uses 32752×8 the position memory structure;
* the read-write number of times reaches as high as 10 11 times, has 10 year data storage ability;
* the quickest parallel reading speed is 70ns, reads in without the time delay;
* has the real-time clock and the calendar function, the clock register in the address space on most 16 bytes place;
* the exterior supplies reserve power source, provides 32.768kHz the time record crystal oscillator;
* has programmable real-time, the calendar clock and the warning time;
* programmable watch-dog timer;
* programmable power source monitoring module.
On the FM3808 chip integrated three kind of different functions: 32k×8B memory cell, real-time clock, calendar function, system monitoring function. Its structure diagram as shown in Figure 1.
3 FM3808 function explanation
3.1 FM3808 real-time clock operation
The real-time clock (RTC) by the crystal oscillator, the clock frequency divider and a system register is composed. The crystal vibration only then in controls the register (7FF8h) the 7th establishment is when 0 can start to work, the clock frequency divider becomes the 32.768kHz signal frequency division 1kHz, and counts take the second as the unit, may use the sign register (7FF0h) and through establishes R and W comes to each solid clock register to carry on reads and writes. The real-time clock needs to provide the power source to be able to work, when power line voltage VDD drops to is lower than supplies voltage VBAK, real-time clock power source by the VBAK supplies. Regarding FM3808, the user may choose with the electric current makes the power source, may also choose with the electric capacity completes the power supply. When use 1000μF electric capacity, its on time may amount to 30 minutes, if uses 0.4μF electric capacity, then on time may be 240 hours.
When symbolized when register’s 2nd (CAL) establishes 1, the real-time clock enters the calibration pattern. In the calibration 栻 on, the INT pin will output 512Hz the square-wave, the user may through survey the INT foot to deviate the 512Hz error to carry on the clock calibration, the calibration error reads in the 7FF8h unit from the user. After carrying on the clock calibration, in calibrates under the temperature each month’s biggest error for ±4.34ppm the minute, through sets at the CAL position is 0 may withdraw from the clock calibration pattern.
3.2 FM3808 monitoring operation
The system monitoring mainly includes: Warning function, watch-dog timer, power source monitor and system outage.
The warning function is the time value which and the system corresponding value reads in using the programming carries on the contrast, if matches, produces through INT interrupts and establishes corresponding flag bit AF is 1. The warning function provides has four kind of match values, respectively be the second, divides, date, is 0 may choose the contrast position through the establishment corresponding position.
The watch-dog timer by may load the counter and the free movement counter is composed, the watch-dog timer’s operating frequency is 32Hz, this time crystal oscillator OSCEN must establish is 0. The timer overflows the value to deposit in 7FF7h. On system when electricity automatic will overflow the value to load to loads the register, this time the free movement counter will start to time. When before counter value and loading value, may through establish the WDS position is 1 comes the reload overflow value, but this time will not have interrupts the production.
The power source monitoring function is compares VDD with three gate voltages compares. These three gate voltage respectively be interrupt gate voltage VINT, the memory stops gate voltage VLO, exterior service voltage VBAK. When VDD achieves the different voltage threshold, the FM3808 internal phase should the function will stop working. FM3808 altogether may have four external interrupt: Watch-dog interrupt, alarm clock interrupt, power source low voltage interrupt and supplies power source interrupt.
3.3 FM3808 memory operation
In the FM3808 logic may divide into 32768×8 the position memory structure, the most above 16 bytes have apportioned on the spot clock’s register. FM3808 carries on the connection through the parallel mouth with exterior microprocessor, its operation and SRAM are very similar. The FM3808 half memory cell divides into 32 blocks, each block is composed of 256 lines and 4 row namely 1k×8 structures. And A0~A7 is the line of choice line, A8~A9 is the row choice line, A10~A14 is the block choice line. FM3808 chip CE cannot earth, this and ordinary SRAM is different. The FM3808 read process is this: In the CE drop along, the address signal is locked saves, and starts a read cycle, hereafter, even if CE will change not to affect this cyclical completion. Because FM3808 needs along to be able to lock in the CE drop saves the address signal, therefore cannot by the CE earth, read succession as shown in Figure 2 effectively.
Before reading the time data, must establish 7FF0.0 as “1″, after reading duration data, should establish 7FF0.0 as “0″. When reads the data, when after the address signal lock saves, in OE permission situation, DQ0~DQ7 output data. FM3808 altogether has two kinds to write the working pattern, one kind is controls by WE, another kind is controls by CE. Writes succession as shown in Figure by the WE control 3.
Although FM3808 request between CE drops, the address signal must have 5ns the time, but the practical application proof, simultaneously outputs CE and the address signal connection is also may. Because the FRAM read-write process will create the change to the interior memory cell, therefore after one time will read or will write, must very quickly to the original data carry on “patching”. “patching” the process when CE is the high level carries on, therefore in a read-write’s operation, CE is the low time cannot be too long, otherwise FM3808 “patching” the original data will create the data missing without enough time. FM3808 stipulated that CE is the low time does not surpass 10μs.
4 and TMS320C5402 guidance connection
On after TMS320C5402 electricity, will inspect the first MP/MC pin the condition, if this foot is the low level, explained that DSP is established as the micro computer pattern, starts the executive routine from the internal ROM 0FF80h address. In the TMS320C5402 0FF80h address place, is depositing a skipping to 0F800h place the execution DSP free lance loading (Bootloader) the procedure instruction. When TMS320C5402 Bootloader procedure, it according to HPI the loading pattern -> serial EEPROM loading operation -> parallel loading pattern -> standard serial port pattern making type →I/O mouth loading pattern order loop check, will decide that which kind of start pattern will carry out.
To take TMS320C5402 as the core digital signal processing system, the parallel guidance loading pattern was most is suitable. The TMS320C5402 parallel guidance loading pattern is the DSP data which corresponds from the outside memory leads the procedure code in the territory area to load to internal DARAM. TMS320C5402 parallel loading flow as shown in Figure 4.
Uses the parallel loading pattern when carries on the load country to the procedure, must act according to parallel loading the form to dispose Flash the program data storage space. May first and in the FFFFH address reads in DSP corresponding data space FFFEH must deposit the procedure the address, then the basis parallel loading’s data stream, after will mark the control word, each register’s initialization value, the loading outset movement address, the segment size and the loading address reads in the Flash stored routine in turn in the address, the electron reads in the compilation finally the procedure.
FM3808 and TMS320C5402 parallel interface design as shown in Figure 5, because the FM3808 work power source is 5V, thus in the system has used SN74LVTH6244 and SN74LVTH2245 completes the connection design. Also because the TMS320C5402 data’s addressing range is the 64k character most greatly, but in oneself do not compile the Bootloader procedure in the situation, the parallel guidance loading pattern most greatly can only load the 32k character the procedure or the data. Therefore, if the program data is bigger than 32k, needs the redesign.
On when TMS320C5402 electricity replacement loading, because Bootloader procedure already in initialization time establishes XF as the high level, thus in after the EPM3202 total logic, TMS320C5402 may unit data read FM3808 in the 08000h-0FFFFh TMS320C5402 to correspond in 000h-3FFFh addressing area internal DARAM. But after the system enters the parallel guidance loading pattern, TMS320C5402 from the data addressing will be the 0FFFFh unit (A15=1, selects procedure memory block first address which Flash) the read is going to write down, will then save the first address place after the procedure to mark the control word, each register’s initialization value, the loading outset movement address, the segment size, the loading address loads in turn to internal DRAM.
If the procedure is big, but in the system must have other data-carrier storage to store the data, then needs to resign the data space which FM3808 takes, this time may use XF in the EPM3202 logical control. And available host disposal procedure’s first sentence RSBX XF sets at the XF pin is the low level, simultaneously causes CE to select patches or strips of land as worth saving for seed invalid, thus resigns the data space. If the procedure is small, but FM3808 must do for the data storage unit, then may establish XF is high, then and reads out through CPLD in logical program control data’s read-. CPLD internal logic as shown in Figure 6.
in 5 designs should pay attention question
(1) this design proposal when TMS320C5402 carries out the Bootloader procedure can the addressing parallel interface FRAM biggest space be the 32k byte, if the off-line independent run-time system’s procedure has surpassed the 32k byte, then can only use other substitution method.
(2) in the FM3808 procedure data stream needs to compile strictly according to the parallel loading data stream, guarantees parallel loading the success. Should through establish SN74LVTH2245 OE and DIR to FM3808 data’s read-in with the read-out completes together, this system is carries on the logical control through CPLD, in fact also the available VHDL language compiles logic.
(3) in the design process, may use in FM3808 the watch-dog electric circuit to come to the systems operation to carry on the monitoring. The system must use FM3808 the low voltage measuring ability, after examining the power failure, CPU should set immediately the CS end level “1″, prevents when on electricity or the power failure in the FM3808 data has the change.
6 conclusions
FM3808 has the high speed read-write, the ultra low power loss and reads in and so on characteristic high performances and the mouth memory without the time limit, its interior integrated the real-time clock and the system monitoring function, has the very strong usability. Through FM3808 and the TMS320C540 composition’s hardware system, may complete the confirmation system’s stability and the FM3808 performance superiority. FRAM reads, merits fast and so on antijamming, low power loss by it, must become one kind to have the competitive power memory.
