Abstract: Introduced the asynchronous communication chip 16C552 function, the characteristic, the structure and the internal register, gave have realized PC machine with the 16C552 chip and the DSP serial communication method, simultaneously has given between them the hardware interface electric circuit and the software initialization routine.
Key word: 16C552; Serial communication; Asynchronous
When realizes PC machine and the DSP serial communication, usually may directly (SCI) the module and the SCI multi-processor communication protocol (i.e. idle line pattern and address position pattern) comes using the DSP serial communication connection in the identical serial line to realize between many processor’s communications, may also use the SCI asynchronous communication pattern to realize the serial communication. Although these two ways can realize the serial communication conveniently, but they must take system many hardware and the software resource, 
thus is not suitable for is quite high to the timely request and the system resources intense application situation. Author in development electric power active filter experiment system, because has used asynchronous communication chip 16C552, thus succeeded has solved this problem. This article will program two aspects from the circuit structure and the software to introduce that this plan will realize the method.
1 16C552 synopsis
1.1 function characteristics and structure diagram
16C552 is the asynchronous communication chip which TI (TL16C552) and VLSI (VL16C552) and so on companies produce, has two enhancement general asynchronous communication unit channels and an enhancement bidirectional printer port; Supports TL16C450 and the FIFO two kind of patterns, its 16 byte FIFO may reduce the CPU interrupt; Each channel has the independent transmission, the receive, the line status and the establishment look-at-me function, simultaneously has the independent MO-DEM control signal, the programmable serial data transmission form (including data position length, verification way, stop position length) and the programmable baudrate generator; Moreover, each channel’s data and the control bus also have the three states of matter TTL actuation function.
TL16C552AM is TI Corporation’s 68 foot PLCC (Plastic Leaded Chip Carrier) seals the chip, its base pin and function diagram as shown in Figure 1. May see from the chart, its serial port mainly completes two functions; first, receives the serial data the peripheral device or the modem to transform the parallel data; Second, transforms the serial data the CPU parallel data in order to transmit. In the normal operation process, CPU may momentarily read 16C552 the status messages, reports the 16C552 transmission operation the type and the condition, including each error status, like parity check, overflow, frame mistake with the FIFO mistake and so on. In addition, 16C552 also has the complete MODEM control function, and has CTS, RTS, DSR, DTR, RI, the DCD equisignal end.
16C552 has a set of perfect interruption system, may establish the priority automatically. Its serial port and the parallel mouth may work independently in interrupt and inquire two workings.
1.2 16C552 internal registers
the 16C552 interior has 12 single byte registers, these registers have taken 8 I/O mouth address, its address decided by A0~A2. And some registers use in common a I/O mouth address, uses in common the I/O mouth may through read/writes a letter the number and the line control register (LCR) the D7 position (DLAB) to carry on the discrimination, the concrete description see Table 1 to arrange in order, what needs to explain: When 16C552 CS0 or CS1 are the low levels, the serial channel can visit.
Table 1 I6C552 internal register
| DLAB | A2 | A1 | A0 | Mark | Register |
| L | L | L | L | RBR | Receive cushion register |
| L | L | L | H | THR | The transmission maintains a register |
| L | L | L | L | IER | Interrupt permission register |
| X | L | H | H | IIR | Interrupt sensing register |
| X | L | H | L | FCR | FIFO control register |
| X | L | H | H | LCR | Line control register |
| X | H | L | L | MCR | MODE control register |
| X | H | L | H | LSR | Line status register |
| X | H | H | L | MSR | MODEM condition register |
| X | H | H | H | SCR | High speed buffer storage register |
| H | L | L | L | DLL | Divisor latch low position |
| H | L | L | H | DLM | Divisor latch top digit |
About the various registers content’s concrete provision, as space is limited, here does not make the specification, some interests may refer to the TI Corporation’s related product material to introduce, but in the serial communication application, must key make clear FCR, LCR, IER and so on several register’s contents. In addition, in the practical application, possibly will sometimes neglect MODEM in the control register’s D4 position, this position for from the test loop return state control position, will use it to be possible to carry on the control to the serial port from the test, therefore, after from the test will carry on finished, but also deals with this position to carry on the replacement, guarantee system’s normal operation.
2 communication system hardware interface circuit
This system’s hardware interface electric circuit as shown in Figure 2. And, the address decoding electric circuit may use the different electric circuit according to the actual need to realize. In order to cause the system use nimble convenient, in this plan uses piece of CPLD to carry on system’s allocation. The reset circuit may use the special-purpose replacement chip, also on available pulls the resistance way to realize. The external connection crystal oscillator may choose voluntarily, then basis crystal oscillator frequency establishment divisor latch’s top digit and low position, thus obtains the communication system correct baudrate, in this system uses the crystal oscillator is 8MHz. In addition, because 16C552A has two serial channels and a standard parallel mouth, their coordination use must perform on the hardware and the software to pay attention. The suggestion will not need the port to select patches or strips of land as worth saving for seed receives the high level (16C552A selecting patches or strips of land as worth saving for seed for low level effective), in order to avoid presents the mistake.
3 serial communication software design
3.1 communication protocols
This design communication protocol including the following several points:
(1) the baudrate is 9600.
(2) the communication order constitutes by 2 bytes: The first byte is synchronized byte 0XFF; The second byte orders the code, mainly uses for to instruct each kind of control command.
(3) each byte including 8 bit data positions and 1 stop position, does not have the verification.
(4) in the communication process, the superior machine to the TMS320F243 transmission synchronization order, after TMS320F243 receives, replies immediately, if reply mistake, then reissues.
when (5) communication procedure to TMS320F243 transmission control command, TMS320F243 returns receive correct answering signal; When communication procedure to TMS320F243 referral system parametric command, TMS320F243 needs the data according to the prescribed form returns.
PC machine and TMS320F243 select the asynchronous communication method, PC machine select the event driven method to receive the data, TMS320F243 use the interrupt mode receive data, but uses the inquiry way transmission data.
3.2 on lower position machine communication software design
Compiles the serial communication procedure on PC machine to have three methods at least, respectively be the assembly language, the C language and the Visual series communication controls (MSComm). Comparatively speaking, the Visual series communication controls to be able to use the few codes with ease highly effective to complete the programming task. In the practical application, available (i.e. VB) 6.0 communications controls MSComm take Visual Basic as the foundation compiles the PC machine serial communication procedure, but uses the assembly language compilation lower position machine (F243) the software. On, lower position machine serial port procedure flow distinction like chart 3 and shown in Figure 4. the 16C552 initialization routine is as follows:
; THE 16C552 INITIALIZATION PROGRAM
C552_INIT:
LDP #00h
SPLK #83h, GSR0
OUT GSR0,0E003h; Establishes LCR
SPLK #34h, GSR0
OUT GSR0,0E000h; Establishes DLL
SPLK #00h, GSR0
OUT GSR0,0E001h; Establishes DLM
SPLK #03h, GSR0
OUT GSR0,0E003h; Establishes LCR
SPLK #08h, GSR0
OUT GSR0,0E004h; Establishes MCR
SPLK #01h, GSR0
OUT GSR0,0E002h; Establishes FCR
SPLK #01h, GSR0
OUT GSR0,0E001h; Establishes IER
RET
Figure 4
4 concluding remark
This article for used asynchronous communication chip 16C552 to realize PC machine and between the DSP serial means of communication conducts the research, the author has developed its serial communication software, and debugs in the experiment passes. This software not only uses nimbly convenient, moreover may realize great data quantity receiving and dispatching using the 16C552 FIFO pattern, thus reduced to the DSP interrupt, alleviated the system resources intense situation.
