Abstract: Briefly introduces one kind of embedded multi-agreement serial communication design proposal from the hardware and the software two aspects. This design proposal uses multi-agreement serial communication controller Z85C30 and the peripheral circuit development, through the software programming, may satisfy each kind of serial communication request, like asynchronous, according to correspondence forms and so on byte synchronization, according to position synchronization.
Key word: Embedded system serial communication controller (SCC) Z85C30
Introduction
We in embedded system’s performance history, need to design frequently serial pass unguardedly, with by exchanges the data with other equipment or the computer network. In view of the different application situation and the different correspondence form, have many different chips in the hardware design aspect to be possible to supply the choice, like Intel 8251A, Intel 8274, Intel 82530 and so on. Uses ZILOG Corporation’s serial communication controller Z85C30 to carry on the design, compares with other components, has the function to be strong, speed quick, external logic few and so on merits.
1 serial communication controller Z85C30 introduction
Z85C30 is one kind of serial communication controller which ZILOG Corporation promotes (SCC). It has the double channel, is suitable in 8, 16 processor’s systems, can complete serial to parallel, parallel to the serial transformation. Z85C30 can process such as the asynchronous form, face the byte synchronized regulations (for example IBM double synchronization regulations), face the bit synchronized regulations (for example HDLC, SDLC); Can produce, inspects CRC circulate the redundant check code.
Z85C30 each channel has 14 to write the register, 7 to read the register. Through to its programming, may satisfy the communication controller disposition each kind of form, like data length, stop position figure, whether there is odd-even check and so on.
1.1 Z850C30 main performance
①Synchronous speed. under the 16MHz clock, the transmission speed reaches 4Mb/s; Uses the 16MHz clock, the transmission speed reaches 1Mb/s (the FM code); Uses the 16MHz clock, the transmission speed reaches 500Kb/s (the NRZI code).
②Asynchronous performance. Each character 5, 6, 7 or 8; 1/2 or 2 stop position; Wonderful or occasionally verifies; 1st, 16, 32, 64 time of clock forms; The break point produces and tests; The odd and even, the overload and the frame make a mistake the test.
③According to byte synchronization performance. In synchronization or outside synchronization; 1 or 2 synchronized character; Automatic CRC has, the test.
④SDLC/HDLC performance. Unusual pause sequence production and examination; “0″ the automatic insertion and the deletion, the text symbolized the automatic insertion, address section’s recognition, the information section surplus management, CRC has, the test; Has the EOP recognition/not to follow the entrance and the export SDLC way; May choose NRZ, NRZI, Manchester or FM arranges/the decoding; Has the clock recovery ability digital phase-locked loop; Has the automatic echo and partial return diagnosis ability.
Moreover, Z85C30 can work highly effective under the SDLC/HDLC way, if has 10×19 position SDLC/HDLC frame condition FIFO,14 the position SDLC/HDLC frame counter, the automatic SDLC/HDLC symbol transmission, automatic reset SDLC/HDLC Underrun/EOM symbolized, initializes SDLC/HDLC CRC automatically and so on.
1.2 Z85C30 main pin synopsis
The Z85C30 pin divides into 7 groups according to the function: The data address main line, the main line succession and the replacement, the control pin, the interrupt control, the serial data, the channel control pin and the clock pin, as shown in Figure 1. Z85C30 pin definition as shown in Figure 2.
D7~D0: The data address main line, uses in transmitting the order and the data.
RD, WR: Reads, writes a letter the number, uses to the Z85C30 register operation, the low level is effective.
CE: Selects patches or strips of land as worth saving for seed the signal.
A/B:A, the B port select, the low level indicated that chooses the B channel, the high level chooses a channel.
D/C: Data/control choice, what the high level expresses and between 85C30 transmits is the data, what the low level expresses and 85C30 transmits is the command signal.
INT: The interrupt request, the low level is effective, when SCC needs to apply for the interrupt, this signal is effective.
INTACK: The interrupt response, the low level is effective.
IEI: Interrupt permission input. The input, the high level is effective. When has many interrupt sources, IEI and IEO compose the interrupt order chain priority lining up electric circuit together.
IEO: Interrupt permission output. The output, the high level is effective.
PCLK: The clock input, uses for the synchronized interior signal, is the standard TTL level signal.
TxD, RxD: The transmission, the receive data, are divided A, the B two channels.
TRxC, RTxC: The channel clock, they can by the programming be several kind of different operation weapons. RTxC can provide receives the clock or transmits the clock (in input mode), can provide the transmission clock counter output (data phase-lock), the crystal oscillator to output, the baudrate generator output and the input clock outputs (them is in output mode). RTxC can provide receives the clock, to transmit the clock, the baudrate generator clock, the digital phase-locked loop clock.
1.3 Z85C30 connection successions
RD and WR are two control signals which the main line transmits. CE, D/C, A/B and INTACK use in the type which the control bus transmits. On the main line transmits address after effectiveness, RD and WR only then change low. CE, WR and CE, the RD lock saves the address the succession is consistent.
(1) read cycle succession
When RD and CE are effective, on A/B and the D/C address is locked saves. CE must maintain low in this cycle, and INTACK must maintain high. The Z85X30 main line actuates the equipment only then effectively only then enables in RD and CE. When reads the operation is high with D/C, will not affect indicator’s condition. When D/C is low, and after the built-in function completes, the indicator repositions to 0.
(2) write cycle succession
When CE and WR are effective, A/B, D/C and at the same time data D7~D0 is locked saves. CE must maintain low in this cycle, and INTACK must maintain high. In writes the operation when D/C is high, will not affect indicator’s condition. When D/C is low, and after the built-in function finished, the indicator repositions to 0.
(3) interrupt response cycle
When INTACK is low, enters the interrupt response cycle. This A/B, D/C, CE, the WR signal is neglected.
1.4 Z85X30 register visit
Visits the register to have two steps, uses the register indicator to complete the addressing. Register which assigns for addressing one, through reads in WR0 the indicator position to assign the register first. Because of Z85X30 only then only register establishment existence, therefore, may read from two channel’s random the indicator. After the indicator reads, once more reads or the write cycle (, when the register which D/C is low) will deposit and withdraw a moment ago assigned. When reads finished with the write cycle, the indicator is repositioned to 0.
To RR8 (receive data buffering FIFO) reading and to WR8 (transmission data buffering FIFO) writes the operation, may carry on according to above method, may also when D/C is high carries on the deposit. When D/C is high, may directly to the corresponding data register carry on the deposit, and indicator’s condition for independent. Thus, permits in one cycle the addressing data register, and does not affect indicator’s condition.
2 Z85C30 and CPU connections
The following introduction by 8051 makes CPU and the Z85C30 interface circuit, as shown in Figure 3.
The Z85C30 clock selects 7.0728MHz. 54LS373 uses for the lock to save selects patches or strips of land as worth saving for seed the signal and the Z85C30 address (uses for to differentiate order, data register). Because Z85C30 writes the succession effectively after the data, only then should present WR the drop along; Before the data is invalid, should present the WR rise along. And 2 opposition component retards with 1 piece of D trigger 54LS74 delivers Z85C30 WR. Because the circuit design is the TTL electric circuit, in actual application, but must join the TTL-RS232 switching circuit chip.
3 software designs
3.1 Z85Z30 I/O operations
X85C30 has three kind of basic I/O operation form: Inquiry, interrupt, block operation. These three kind of I/O operation when initialization and data transfer involves to the register operation.
Inquiry way dependence software inquiry serial controller, thus when decides the data should from the serial controller input or the output. In this pattern, advocates the interrupt to enable the position and the WAIT/DMA request position should program is 0, thus eliminates any interrupt or the DMA request. The inquiry is through carries on to the RR0 condition examination. In this pattern, look-at-me function expiration. Before changing over to the data processing, must read the analysis to RR0, decided that enters what kind of routine.
In interrupt mode, serial controller’s each channel including three interrupt sources: Receiver interrupt, transmitter interrupt and exterior/condition interrupt.
The block operating mode may in the W/REQ output and the WR1 ready/request position coordination. Through the programming, the W/REQ output in the block operating mode can by the definition be the WAIT signal, may take the REQ signal in the DMA way.
3.2 software’s compilations
The different application situation, is different to the Z85C30 initialization flow, this needs to write the register to Z85C30 to entrust with the corresponding starting value.
Figure 3 8051 and Z85C30 interface circuit
After the SCC initialization completes, then carries on the correspondence. Transmission buffer and receive buffer completely for spatial. The software will write about the 1st transmission character transmits the buffer, the interrupt will only then produce. 1st transmission character to SCC shift register, transmission interrupt production. Then, SCC continues to judge the interrupt, until end of message. When end of message, should carry out the replacement transmission interrupt assignment command, used for to forbid to transmit the request interrupt. SCC will examine the last character, the interrupt will stop, will write until other text transmits the buffer.
Register RR2 uses for to explain the interrupt vector sum condition, it from B channel read. RR3 interrupts the evaluation register, uses for to instruct the interrupt the type, it from A channel read. Looked that the network supplemented the version (www.dpj.com.cn) has listed the Z85C30 interrupt flow.
The outside/condition interrupt source includes: The break point/exceptionally interrupted, the transmission to owe carries/the end of message interrupt, the CTS interrupt, the synchronized/search interrupt, the DCD interrupt, zero counting interrupt. It by WR1 and WR15 establishment, only then in after WR1 exterior/the condition interrupt permits in the position and the WR15 corresponding control position setting, the outside/condition condition will only then have the interrupt.
Conclusion
Uses this design proposal, can satisfy the different correspondence form the request, the software programming may act according to the actual situation to select the inquiry way, the interrupt mode, the DMA transfer method, if needs to be possible to add the MODEM control mode. Because the Z85C30 function is formidable, in many embedded systems, the network design aspect, selects Z85C30 to carry on the development as the communication controller, can definitely realize its anticipated function.
