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   Abstract: Mainly introduced that one kind realizes the double DSP system using the Flash memory to have the method which to many user codes the choice on electricity loads. And, introduced with emphasis M29W800AB Flash the use and programs the method, the TMS320VC54X DSP on electricity automatic guidance process, as well as HPI pattern and parallel pattern load user code method.

    Key word: Flash memory DSP host interface Bootloader guidance table

Introduction

　　In TMS320C54X in series DSP system’s development, because DSP internal only then ROM and RAM memory, if must read in the user code in ROM, must complete by the DSP chip factory; But is the user not to be able like this to change the code again, is very impractical. Because RAM after the DSP power failure cannot preserve the data again, therefore, using EPROM, Flashand so on some exterior memory deposits the user code frequently. After DSP electricity work, provides the boot mechanism using DSP, downloads again the procedure to DSP RAM in moves. If uses the EPROM exterior memory depositing user code, needs to use the code conversion tool the user code conversion for the binary system object file, then interpolates with the programmer its fever EPROM; But if uses the Flash memory depositing user code, then may use the DSP simulator and CCS directly (Code Composer Studio) the simulation environment carries on the online programming, use nimble convenient, no longer needs other programming equipment. In some ethernet communications system, we use the Flash memory to realize many user codes to have the choice load. Below take this system as the example introduced that loads the method to the TMS320VC54X DSP one kind of user code.

1 system skeleton

牐 牬 delivers ㄐ the bank lowly chen in 802.3 ethernet standards, with realizes between various terminals voice and other data correspondence, as well as realizes in the local area network the terminal and the outside voice and the data communication. In order to save the development cost, enhances system’s extendibility, the versatility and the flexibility, we the terminal use the same hardware construction to each net, causes it through the use different software code to realize the different function, plays the different role.

牐 犆 bright ㄐ cuts sou 2 components fat earnestly and so on DSP chips, 1 network card, 1 CPLD and 1 FPGA as well as Flash memory composes the expandable basic structure. And, achievement advocates CPU by TMS320VC5410 the DSP, is responsible for system’s logical control and the general data transmission; Takes by MS320VC5416 DSP from CPU, is responsible for the voice arrange work and so on decoding and echo cancellation, pronunciation examination. between 2 DSP (HPI) carries on the correspondence through the host interface. In order to realize the code to have choice downloading, may dispose a port achievement by FPGA to dial the code switch, causes the user to dial the code switch through the adjustment, may have choice downloading to save in Flash the user code, its structure as shown in Figure 1.

牐 犈 washes with watercolors the appearance Beta wo pass is to expand system’s function, realizes hardware platform multiple functions. We may realize the different function many user code to read in the Flash memory to deposit, dials the code switch’s establishment through the hardware, a choice user code downloading execution. When system electricity load user code, the system downloads the FPGA disposition procedure first from Flash, then dials the code switch’s value through the FPGA read-out, then acts according to this value to choose corresponding from Flash 5410 DSP user code load; But 5416 DSP user code loads are complete in 5410 code loads, after start movement, reads out the corresponding 5416 codes by 5410 procedures from Flash, loads again through HPI to 5416, realizes 5416 DSP code loads and the start by this.

2 M29W800AB Flash memory introduction and use

牐 犜 cheats disputed those who hold the school we to select lowly is M29W800AB the Flash memory, its capacity for 512K×16 the position, divides into 16 pages, each page of 32K. And, the 0th page has 4 modules: 0×00~0×1fff, 0×2000~0×2fff, 0×3000~0×3fff, 0×4000~0×7fff. Other each page, each page is 1 module, altogether has 19 modules.

牐 牰 訤 the lash operation must depend reads in a series of specific addresses and the data series completes. In each time reads in before Flash, must carry on the cleaning to its original content. The Flash cleaning cleans two kinds including the block cleaning and the chip. The block cleaning is carries on the cleaning to a module, the chip cleaning is the cleaning entire Flash content. Therefore, to the Flash operation, is take the module as the elemental area. Decided to the Flash operation by the instruction that its must satisfy Flash the succession request, each instruction needs 1~6 different instruction cycles. The main operational order including reads the data command, the programming instruction, the reset instruction, the automatic selection instruction and the cleaning instruction. Each instruction cycle by an order constitution, the duty like table which each order code carries out 1 arranges in order.

Table 1 Flash order explanation

牐 犗 the travel plays 訫 the 29W800AB Flash block cleaning instruction is an example, explains Flash specifically the operation succession: The block cleaning instruction needs 6 bus cycles, starts first by 2 release periods, is 1 cleaning establishment cycle, then is also 2 release periods, finally is 1 cleaning acknowledge cycle, its instruction succession like table 2 arrange in order.

Table 2 Flash cleaning instruction explanation

牐 犉 the cesium language programming code is as follows:

#define flash ((volatile unsigned int*) 0×8000)

Block_Erase(ADDR) {

flash[0x5555] = 0×00AA;

wait(1000);

flash[0x2AAA] = 0×0055;

wait(1000);

flash[0x5555] = 0×0080;

wait(1000);

flash[0x5555] = 0×00AA;

wait(1000);

flash[0x2AAA] = 0×0055;

wait(1000);

flash[ADDR] = 0×0030;

}

What 牐 犘 chessboard attention is, when Flash was opposite in DSP is the slow equipment, the programming, needed to have the enough time delay waiting visit to Flash. 11 did not introduce to other instruction here. Must understand that more contents, may refer to the concrete Flash memory handbook.

3 guidance loading

牐 candle MS320VC5410 and in TMS320VC5416 internal ROM the solidification has the TI Corporation’s guidance to load the (Bootloader) procedure, uses when on electricity replacement guides the user code from the exterior memory to internal RAM to move. The vectoring procedure is in a some internal solidification procedure, it is responsible for on when the electricity initialization memory. In other words, it (for example the Flash memory) calls in the procedure from the nonvolatile storage in system’s memory. It provides the internal guidance pattern includes: HPI (host interface) guides, the parallel EPROM guidance, the parallel I/O guidance and the serial port guidance and so on. Below introduces these two chips first on electricity guidance process.

After 牐 燚 on SP electricity replacement, examines its MP/MC pin first, if MP/MC= “0″, indicated that use internal ROM guides. This time, DSP starts from 0xFF80 place to carry out the TI internal vectoring procedure. After entering the vectoring procedure, the HINT pin becomes the low level, then starts to examine INT2 whether for low level (effective). If effective, enters the HPI guidance way; Otherwise, examines the INT3 pin. If has the INT3 request interrupt, enters the serial guidance way; Otherwise, enters the parallel guidance way. In this system, we use the Bootlooder procedure which TI Corporation provides to carry on the guidance loading, for this reason, should meet the MP/MC pin the low level. Vectoring procedure flow as shown in Figure 2.

    3.1 HPI patterns realize the TMS320VC5416 program load

牐 牥 falls the immortal scoop weary 5416DSP program load to use HPI hastily (host interface) the pattern. Regarding the HPI guidance pattern, must HINT and the INT2 pin connects in together, guaranteed the Bootloader procedure can examine INT2 to be effective. When examines it for the low level, enters the HPI guidance way. After main processor 5410 start movements, 5410 procedures download 5416 procedures from Flash, reads in 5416 RAM through 5410 and 5416 between HPI. In reads in the procedure 5416:00, must defer to 5416 procedures the cmd document dispositions, the code which reads out from Flash will read in 5416 procedure spaces the code section. After finishing the code, but should also read in 5416 code start addresses 5416 0×7f units, 0 read in the 0×7e unit, the start address may translated 5416 codes after the CCS simulation environment see, this time PC aimed the position was the code start address. This is because, when after 5416 enter the HPI guidance way, the Boodloader procedure starts to examine the 0×7f unit the content (0×7e and 0×7f two unit contents when the Boodloader procedure starts carries out reset). When examines its content is not the zero hour, soon the 0×7e content bestows on for XPC, bestows on the 0×7f content for PC, the procedure skips to the PC bearing execution user code. This has realized from the piece 5416 program load start. Figure 3 is the HPI pattern load user code flow.

    3.2 parallel load patterns realize the TMS320VC5410 program load

牐 5410 main processor’s user code loads use the parallel pattern load. In this system, has many 5410 user codes to save in Flash. On after system electricity, must download the FPGA disposition code first from Flash, then the read-out dials the code switch’s value, then chooses corresponding user code downloading, after completing, skips starts to the user code entry point address to carry out the user code. Therefore, needs to design a start-up procedure to realize the above function. Start-up procedure’s content including downloads the FPGA disposition code, reads pulls out the code switch value, and according to this value choice downloading corresponding 5410 user code to its cmd document disposition corresponding procedure space. After completing, skips to the user code start address. Code start address after CCS simulation environment translation obtains, start-up procedure downloading movement, then must depend upon TI the internal vectoring procedure, uses 16 bit parallel pattern guidance to load, needs to construct the guidance table. The so-called guidance table is the code which the vectoring procedure must call. Guides in the table besides to include the source code, but also contains some extra message. These information instruction vectoring procedure concrete implementation. Therefore, may say that the guidance table is one kind of construction of data which is composed of the procedure code and some extra message. In here, we need to use the start-up procedure construction guidance table, and will guide the table also to read in Flash.

牐 犜 cheats disputed that holds the school presently the lash memory mapping is the DSP 0×8000~0xffff data space lowly. When to the Flash operation, must first choose the page, each page corresponds is the DSP 0×8000~0xffff address data space. Needs to pay attention: Besides will guide the table to read in Flash, but should also guide the table the start address (address which speaking of the DSP processor, if in Flash is 0, to DSP is 0×8000) reads in the Flash first page of last unit (the 0×7fff unit), namely DSP storage space 0xFFFFh unit.

After 牐 犚 the master program enters the parallel load pattern, will inquire the data space 0xFFFFh unit, until reads in an effective address data. This data for user guidance table entry point address. By now, the vectoring procedure skipped to Flash in the user guidance table starts to carry out. What needs to pay attention, regarding the different model and factory Flash, its guidance table’s form and the content is different. Below the contents note which guidance table’s form and we disposes on M29W800AB the Flash is as follows:

牐 牫 the ribbon rui downloads according to the guidance table’s content the user code to the procedure space which assigns, and will assign the procedure entry point address value bestows on for PC, makes the procedure to start from here to carry out, thus completes 5410 DSP the guidance starts. Parallel guidance flow as shown in Figure 4.

牐 犜 knows by heart low Che Naidao really to have a nightmare in the resentful regulation, when loads 5416 codes through HPI, must pay attention to 5410 and 5416 clocks must match. Generally speaking, requests from above piece clock primarily piece clock’s 1.25 times. In this system, the system datum clock is the 8MHz,5410 start clock supposes is 8MHz,5416 supposes is 10 frequency multiplication 80MHz.

牐 牨 Ju Dichi she earthworm flexure Kangqiao Zhisou trades multipurpose, expanded system’s function, strengthened system’s flexibility and the versatility, has made the good progress in the practical application.