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Abstract: AT93C46/56/66 is the low power loss which, the low voltage, the electricity Atmel Corporation produces may clean, the programmable non-erasable storage, uses the CMOS processing technology to make and to have 3 serial interfaces, its capacity respectively is 1kB/4kB, may duplicate again 1,000,000 times, the data may preserve above 100 years. In the article introduced this memory’s pin function and the instruction succession, have given AT93C46/56/66 and monolithic integrated circuit’s connection application electric circuit and the software routine. Key word: EEPROM memory interface application procedure AT93C46/56/66 16 monolithic integrated circuits are suitable for the high-speed control situation and the function by it many and so on merits have seized certain market in the industrial control domain. Because EEPROM can, in is not separated from system’s situation to revise in its memory cell the content, therefore is getting more and more widespread in 16 monolithic integrated circuit’s applications. This article unifies 16 machine characteristics, introduces AT93 in detail series EEPROM and the application method. The programmable non-erasable storage which AT93C46/56/66 is ATMEL Corporation promotes the low power loss which, the low voltage electricity may clean. It uses the CMOS technology and Fairchild Semiconductor Corporation’s Mi-croWire industrial standard 3 serial interfaces, has the 1kB/2kB/4kB capacity, and may dispose 128×8/256×8/512×8 or 64×16/128×16/256×16 isostructuralism through the ORG base pin. This series memory reliability is high, can duplicate writes 1,000,000 times, the data may preserve 100 years not to lose; Uses 8 foot PDIP/SOIC seal and 14 foot SOI seal (the SOI seal is JEDEC and the EIAJ standard), compares with parallel EEPROM, AT93C46/56/66 may save the board space greatly, and the wiring is simple, thus has the broad future in the multi-purpose precision reflectoscope reflectors. 1 pin function AT93C46/56/66 memory chip’s pin arrangement as shown in Figure 1. Various pins’ function is as follows: CS: Selects patches or strips of land as worth saving for seed the signal. The high level is effective, when low level enters the waiting pattern. Between the continual instruction, the CS signal must continue at least the 250ns low level, can guarantee the chip normal work. CLK: Serial clock signal. In the CLK rise along, the operation code, the address and the data position enters the component or outputs from the component. When transmits the sequence, CLK should better not stop, prevents to read/writes the data the mistake. DI: Serial data input. May input under the CLK synchronization starts the position, the operation code, the address position and the data position. DO: Serial data output. When the CLK synchronization read cycle, uses in the output data; But when the address scratches/the write cycle or the chip scratch/the write cycle, this end uses in supplying the busy/idle information. VSS: Earth. VCC: Meets the 5V power source. ORG: Memory structure disposition end. When this termination VCC or is hanging, the output is 16; When meets GND, the output is 8. NC: The spatial foot, does not connect. Table 1 AT93C46/56/66 system instruction
In table, 93C46 n=6; 93C56n=7; 93C66n=8 2 instructions and succession At93C46/56/66 instruction like table 1 arranges in order, the various instructions’ concrete meaning is as follows: (1) scratches/writes the permission instruction (EWEN) Because after on electricity replacement 煟 grain of abundant stem Chang Mangchu will bite 56/66 will first be at scratches/writes does not permit the condition. Therefore this instruction must carry out before all programming pattern, once after this instruction execute, so long as the outside does not have the power failure to be possible to carry on the programming to the chip. (2) the address scratches the instruction (ERASE) This instruction uses in forcing to assign in the address all data position is “1″. Once the information carries in DI is decoded, must make the CS signal maintains at least the 250ns low level, then sets at CS for the high level, the DO end will instruct by now “busily” the symbol. DO is “0″, indicated that the programming is carrying on; DO is “1″, indicated that should assign address the register unit to scratch, may the execution next instruction. (3) the address writes the instruction (WRITE) When writes the instruction, writes the address first, then fools 16 熁 Ying Gan 犑 according to reads in assigns in the address. After DI end output last data position, in CLK clock’s next rise before, CS must for low, and must maintain 250ns at least, then sets at CS for the high level. What needs to explain: When write cycle, writes a byte to need time-consuming 4ms every time. (4) the address reads the instruction (READ) Reads the instruction to use from in the unit which assigns the data from the top digit to the low position output to the DO end, but logic “0″ the position is before the data position output. Reads the instruction in the CLK rise along triggering, and must pass through period of time to be only then stable. In order to prevent to make a mistake, suggested after reading the instruction had ended, then outputs 2~3 CLK pulses. (5) the chip scratches the instruction (ERAL) This instruction may set entire memory array is 1, other functions and the address scratch the instruction to be the same. (6) the chip writes the instruction 煟 to wish the remote grain ta This instruction may order the data which assigns to read in the entire memory array, other functions and the address write the instruction to be the same. This instruction cycle spends the time the maximum value is 30ms. (7) scratches/writes the inhibit command (EWDS) Uses this instruction to be possible for the data which reads to carry on the protection, the sequence of operation with scratches/writes the permission instruction to be the same. 3 AT93C56 applications 3.1 AT93C56 and 80C196KB connections Serial EEPROM chip AT93C56 with 80C196 monolithic integrated circuit connection’s hardware circuit connection method as shown in Figure 2. In chart, because MCS-96 series 16 monolithic integrated circuit’s P1 mouths for standard bidirectional mouth, therefore, to prevent the data dislocation, when writes the data to its P1 mouth, must set the first P1 mouth “1″. 3.2 software programming Should read/writes the procedure to use the PL/M language compilation, because the PL/M language is situated between the higher order language and the assembly language, therefore it to the data, address position’s processing is quite tedious. And ADDR is the address unit which assigns, DATA is the data which reads, when writes the data, the address from top digit start. This procedure has debugged on the simulator passes. And has been applied in the electric quantity reflectoscope reflector (for example contact resistance reflectoscope reflector). DECLARE SETCS LITERALLY `CALL BITSET 煟 IO-PORT2,0 牎 lie DECLARE CLRCS LITERALLY `CALL BITCLR 煟 IOPORT2,0 牎 lie DECLARE SETCLK LITERALLY `CALL BITSET 煟 IOPORT2,5 牎 lie DECLARE CLRCLK LITERALLY `CALL BITCLR 煟 IOPORT2,5 牎 lie DECLARE SETDI LITERALLY `CALL BITSET 煟 IO-PORT1,5 牎 lie DECLARE CLRDI LITERALLY `CALL BITCLR 煟 IOPORT1,5 牎 lie EWEN:PROCEDURE PUBLIC; DECLARE I BYTE; CLRCS; CLRDI; CLRCLK; SETCS; SETDI; SETCLK; DO I=1 TO 2; CLRCLK; CLRDI; SETCLK; END; DO I=1 TO 2; CLRCLK; SETDI; SETCLK; END; DO I = 0 TO 6; CLRCLK; SETDI; SETCLK; END; CLRCLK; CLRCS; SETCS; SETCLK; CLRCLK; END EWEN; READ:PROCEDURE (ADDR) PUBLIC; DECLARE (ADDR, I, COUNT) BYTE; CLRCS; CLRDI; CLRCLK; SETCS; DO I= 1 TO 2; CLRCLK; SETDI; SETCLK; END; DO I =1 TO 2; CLRCLK; CLRDI; SETCLK; DO COUNT=1 TO 7; BITOUT (COUNT) =SHR (BITOUT (COUNT), 1); END; CLRCS; CLRDI; CLRCLK; CALL TIME (100); SETCS; CLRC; END READ; WRITE: PROCEDURE (ADDR, DATA) PUBLIC; DECLARE (ADDR, DATA) BYTE; CLRCS; CLRDI; CLRCLK; SETCS; SETDI; SETCLK; CLRDI; CLRCLK; SETCLK; SETDI; CLRCLK; SETCLK; END; DO I =-1 TO 8; X=ROL (ADDR,1); ADDR=X; CLRCLK; IF ((X AND 01H) =01H) THEN SETDI; ELSE CLRDI; SETCLK; END; DO I =1 TO 7; CLRCLK; SETCLK; END; DO I =1 TO 8 CALL BITSET (.IOPORT1,7); COUNT=COUNT-1; CLRCLK; SETCLK; BITOUT (COUNT) =IOPORT1; END; CLRCLK; SETCLK; J=0; AA: DO I= 1 TO 8; J=J 1; X=ROL (ADDR,1; ADDR=X; CLRCLK; IF ((X AND 01H) =01H) THEN SETDI ELSE CLRDI; SETCLK; END; IF J<>16 THEN DO; ADDR =DATA; GOTO AA; END; CLRCS; SETCS; CALL TIME (100); END; |
