This article to you will introduce that a section uses the optical fiber channel protocol to realize the RAID controller’s system design plan. How will we discuss with emphasis use Anjielun Tachyon 4 Gb/s 4 port optical fiber channel protocol IC, many floppy disk channels joins, in provides the RAID application in the computing system, and for uses the RAID storage technology the overall system to carry on the simple introduction (including optical fiber channel analysis situs and option, FC terminal, floppy disk channel and processor function).
RAID system construction outline
Data storage’s application is getting more and more widespread. Past sole equipment holds or has the massive numerical information now. The mass data time’s arrival has accelerated the people the demand which saves to the information security. Time slide by, the people have preserved the massive data, but obtains the loss the data actually to spend greatly. Therefore, the people had deployed the reliable data access system preserves or the stored datum. Along with protection data security call’s surging upward, also day by day increases to the RAID solution’s demand. The RAID solution provides has many kinds of is helpful in raising the data retrieval success ratio the selection scheme. Although the RAID technology has been possible to apply now in realizes on any digital storage medium which the reliable retrieval needs, current people generally data storage on physical medium.
In implements the RAID technology in the complete system, needs to consider the following item:
* brings or many CPU control processors.
* needs connects some floppy disks and the control processor. Usually uses uses in attaching driver’s special agreement specially to realize the floppy disk connection. At present, has several kind of popular floppy disk agreements. Here we will introduce that with emphasis uses the optical fiber channel protocol in the majority high-end memory array design.
* between the driver and the processor is unable to realize the highly effective connection directly. Therefore, the people have used the protocol converter are on a connection processor provide API, and realizes with another connection on driver’s connection.
Figure 1 is the canonical system demonstration, including four CPU, the array which by the memory controller and the interface equipment is composed the processor group which (Processor Complex), an agreement controller and many optical fiber channel link composes. To the floppy controller construction’s multiplicity and the advantages, this article does not make the discussion. Shown in Figure 1 the system for the simple the general construction, we will use it to introduce the RAID controller’s general function.
RAID outline
RAID implementation plan this concept and not only includes the stored data which the later retrieval needs, it also involves to uses as follows introduction first-level or many machine RAID constructions.
RAID-0: Data division (Striping). The data division cannot increase the system safety, but may enhance the system performance. A document is saved on many drivers. The document is divided into certain, and is read in turn in the continual floppy disk, like this may share the single driver to write the reaction time and to cause many to write operation overlapping to carry on.
RAID-1: Floppy disk mirror image (Mirroring). Duplicates in completely another floppy disk a floppy disk’s on all data. This need reads in the data in the different floppy disk, involves independent writes the operation to two. These two floppy disk dereliction next best minute, a floppy disk is the another floppy disk 100% backups. Has completed writes the operation, must be at the same time has completed on two floppy disks same has written the operation. If a floppy disk breakdown, maintains the normal operation with it mirror image’s floppy disk, will not create interrupts. RAID-1 has provided the good managed capacity, moreover when normal operation or system recovery does not need to take too many CPU. But this way cost is very big: On the floppy disk needs to protect each milliardfold byte can need a completely entirely alike milliardfold byte. In other words, RAID-1 needs the floppy disk space is non-protection floppy disk space two times.
RAID-2: Hamming code error correction (Hamming code error correction). Is the same with the ECC memory, RAID-2 also used the hamming code method to verify the floppy disk data the accuracy.
RAID-3, RAID-4 and RAID-5 have used the different parity check method. Duplicates the data with RAID-1 to be different completely, these rank’s RAID through increases an additional disk to disperse the data on several floppy disks. On additional disk’s data is calculates with other floppy disk’s data (uses Boolean XORs). When in floppy disk group any loss, may use in the floppy disk group on other floppy disk’s data to resume the loss through the computation the data. Because these methods do not need the RAID-1 100% floppy disk backup the expense, therefore they need the cost to be lower than RAID-1. However, because on floppy disk’s data is calculates, after the floppy disk loses, will affect with writes the operation and the data recovery related performance.
RAID-3: Virtual disk block (Virtual disk blocks). RAID 3 will disperse the data write operation to the RAID array on all floppy disks carries on (data division). Because each time writes the operation to contact each floppy disk, at the same time the array can only read in together the data, therefore causes the entire RAID system performance to drop. The RAID-3 performance because of writes the operation nature the difference and the difference: Reads when the few data because of needs all floppy disk work, the performance is bad, but when reads in the mass data the performance is good.
RAID-4: Special-purpose wonderful coupling (Dedicated parity disk). In the RAID-4 array, some group of data plate, usually is 4~5 data plates (may have more data plates, but will affect performance greatly) and uses for to manage on specially other floppy disks the data odevity special floppy disk. Because each time writes the operation to need to visit the wonderful coupling, the wonderful coupling has become the system performance bottleneck, reduced in the entire array to write the operation the speed.
RAID-5: Floppy disk division (Striped parity). RAID-5 is in fact same as RAID-4, what is only different: In RAID-4, all parity check information located at a sole floppy disk on, but in RAID-5, has carried on the division to the parity check information, deposits it in the array on each floppy disk. This kind of sharing may balanced and reduces the RAID-4 method the performance influence. In commonly used RAID-5 software implementation plan, because wrote the operation to take 15% above floppy disk space, the system speed will become very slow, made one accept with difficulty.
Must implement willfully the RAID combination, needs to consider several functions. When implements 0 level of above RAID plans, usually must connect many floppy disks. In order to realize the data division, the mirror image and the parity check, has used many kinds of disk accessnig way ‘OR’ operation. For example, to realize RAID-1, needs to approach two driver write data continuously. The floppy disk reads or writes the operation usually to call it the floppy disk input/output (I/O). This may be may realizes the correspondence random agreement with or many drivers. This function may the software which or on many processors moves through the system in realize. The method is when realizes through agreement controller API the RAID technology and carries on the correspondence, realizes the high-quality floppy disk to read in the function.
Should better use one to be possible to manage many floppy disk channel’s agreement controller, causes to process the cybertron to be possible, in RAID applies in the neutral system administration function to work. And so on complex agreement speaking of the deployment connection condition and many driver channel’s optical fiber channel, usually the use is similar in the Tachyon serial products high-end controller provides the highest rank for the system the performance.
Tachyon construction
The Tachyon optical fiber channel protocol controller serial products has used 1 Gb, 2 Gb and 4 Gb optical fiber channel link, and passes PCI, PCI-X or PCI according to the different equipment the Express connection and the system is connected.
No matter although is the optical fiber channel technology, the system bus interconnection technique has made the significant development, the Tachyon agreement engine system construction is actually develops along with the semiconductor processing technology development. This construction (Finite State Machine) designs take FSM as a foundation. In the FSM design, has used the numerous independent state machines, these state machine parallel running, therefore may obtain compared to the firmware or a software solution higher performance. Increases along with the frequency, the Tachyon performance also correspondingly enhances, but in based on firmware’s solution, the channel frequency will not improve the algorithm directly the performance.
The Tachyon construction support joins a gambling game and leaves office the data path independence and the synchronized movement, therefore may realize the full-duplex under the optical fiber channel link entire speed to operate. In addition, because may the synchronous processing I/O operation control request while data migration’s that the Tachyon construction may also realize the data mobile equipment’s best use.
The FSM performance and the clock rate are closely related. Not only the FSM design may decide each clock cycle, moreover with embedded microprocessor equally when the issue instruction and the data look takes to the memory access speed do not have the dependence. Except promotes along with the link performance processing technology’s development, Tachyon also increases each second I/O performance using the system interface bus’s technical change.
PCI Express serviceability
In the past, the bidirectional system bus connection (for example PCI and PCI-X) the shared resource has limited in the Tachyon construction full-duplex function. In the Tachyon product two independent data mobile equipment struggles takes PCI or the PCI-X system connection.
Has independent Ingress and Egress data path link PCI Express is suitable for the Tachyon construction. As a result of Express the Ingress data path and the Tachyon outgoing data path as well as Express the Egress data path and the Tachyon join data path’s union use, the data may the bidirectional free transmission, this be simultaneously consistent with the Tachyon construction original intention.
Was a pair of unidirectional link also eliminated from a bidirectional system bus transformation with the connection transaction related loss bus cycle, this time, had a waiting returns data request in the main line (i.e. register to read). In addition, because PCI Express is a serial link technology, requested that may use the pipeline technology to process. May use the goal equipment’s performance well massively after the pipeline technology processing request.
Because PCI Express and the Tachyon optical fiber channel controller is the same, may provide geminate the bidirectional serial link, therefore may use each second each link direction transmission the byte count to express the band width connection performance. A group (lane) PCI Express is the 2.5Gb/s unidirectional serial link is composed, after arranging the decoding, each direction each second by two speeds may process 250 Mbytes. Serial products (QX4 and QX2) may dispose using PCI-E the technical Tachyon are 1 group, 4 group or 8 group PCI Express, therefore may provide reaches as high as 4 Gbytes to pass on the band width or the unidirectional 2 Gbytes band width mutually. Table 1 shows is the Tachyon serial products band width demand and PCI the Express performance match situation:
Table 1:Tachyon band width request and PCI Express performance match situation
May see from the previous table, when PCI the Express connection’s use factor has achieved 80%, 8 group PCI Express says theoretically may support QX4 (4 4 Gb optical fiber channel link) under entire link speed all 4 functions. Supported many 4 group Express link PCI the Express root unified body (root complex) to be possible connected (each equipment 4 group PCI Express) and may obtain 2 Gb/s with two QX2 equipment on all 8 ports the entire optical fiber channel link speeds, the use factor has achieved 80%.
Is precisely as a result of the PCI Express serial link attribute and the Express flexibility, PCI Express becomes is suitable for the Tachyon optical fiber channel protocol controller serial products best system interface bus. PCI Express agreement compatibility backward, because might realize the driver compatible to simplify transfers PCI Express from PCI or the PCI-X system interface bus the decision-making process.
The use looks like the equipment which Tachyon integrates like this highly, may construct the high performance with the ready-made module standard the RAID system. Using processor’s variability and memory design, so long as uses the ordinary system software investment, may adjust the target system application solution the performance, causes it to transform from low end SMB into the high-end data central array.
Current PCI Express performance
Introduced PCI on table the Express main line’s original bedding rate performance. And, does not have the consideration and PCI the Express related expenses. PCI the Express correspondence mainly (TLP) is composed of the processing level data packet. Each processing level data packet (TLP) contains the correlation data as well as the article article and other smooth track/error detection information. Besides processing level data packet (TLP), but also has the data link layer data packet (DLLP). The data link layer data packet (DLLP) mainly uses in the ACK/NAK agreement as well as the class control mechanism (Flow Control Mechanisms). In addition, but also has the physical level data packet (PLP), but the physical level data packet (PLP) mainly uses in the preliminary function and the bad way operation, like link training (link training) and province electricity pattern.
Each processing level data packet (TLP) the system expenses are big. It by the article article, CRC and other information is composed. Because each processing level data packet (TLP) has the fixed system expenses, the big processing level data packet (TLP) may use the system bus well. If supposition and processing level data packet (TLP) quantity compares, data link layer data packet (DLLP) and physical level data packet (PLP) quantity may ignore, we may use the processing level data packet (TLP) the size calculates PCI-Express the most Dali to discuss the band width. In table 2, we to use the QX4 performance which PCI the Express theory band width obtains with soon available (in January, 2005) PCI the Express root unified body (Root Complex) supports each kind of processing level data packet (TLP) has carried on the contrast.
Table 2: Obtains the QX4 performance compares with each kind of different size processing level data packet’s PCI-Express theory band width
In table 2, supposition not with the FCP correspondence, Tachyon construction of data or Tachyon register deposit related expenses. These theory value also supposition PCI-Express root unified body’s standby period is zero. Obtains QX4 1.1 values including FCP current capacity expenses, Tachyon construction of data and register deposit expenses as well as PCI Express standby period.
Under the half-duplex operation disposition (crown only to a direction transmission), the link control data link layer data packet (DLLP) transmits to the data processing level data packet (TLP) the reverse direction, will therefore not reduce the system performance. After introducing the full-duplex, the flow control data link layer data packet (DLLP) and the data processing level data packet may share same PCI the Express simplex channel; Any flow control data link layer data packet (DLLP) can cause the data processing level data packet (TLP) transmission delay. Reiterated once more, all theory band width tentative data link level data packet (DLLP) and physical level data packet (PLP) the influence ignores.
The above related band width’s discussion, elaborated how to act according to 4 Gb optical fiber channel equipment to carry on the promotion to PCI Express. And 512 byte I/0 this value which might complete in one second (each second I/O) has carried on the definition with an equipment to IOPS. The IOPS observed value may also promote along with the PCI Express promotion.
We use current available PCI the Express chip collection and single Anjielun QX4, discovered that IOPS the value surpasses 1.3 MIOPS (Figure 3). Changes along with the processor speed quick as well as may support the bigger processing level data packet (TLP), estimated that we may see a better performance.
Chart 1:RAID controller function simple construction canonical system demonstration
Figure 2: Independent Ingress which and the Egress circuit provides with PCI Express carries on the contrast to PCI and the PCI-X bidirectional bus system connection. As a result of Express the Ingress data path and the Tachyon outgoing data path as well as Express the Egress data path and the Tachyon join data path’s union use, the data may simultaneously the bidirectional free transmission.
Figure 3: Uses the I/O size which Anjielun QX4 Tachyon optical fiber channel controller IC and present available PCI the Express chip collection institute obtains with according to the order to read contrast of the IOPS
