1 introduction
Along with the digital signal processing technology’s unceasing development, the large capacity programmable logical component’s unceasing emergence, the FPGA technology more and more applies in the large scale integrated circuit design. In this hardware system design, will meet frequently needs the large capacity data storage the situation, below we will aim in FPGA internal Block the RAM limited shortcoming, proposed will unify FPGA with exterior SRAM improves the design the method, and has given the part VHDL procedure.
2 hardware designs
Here mainly will discuss take Xilinx Corporation’s FPGA (XC2S600E-6fg456) and ISSI Corporation’s SRAM (IS61LV25616AL) as the main component completes the large capacity data storage the design mentality.
FPGA is the scene programmable gate array, its structure and the traditional gate array is similar, the massive programmable logical block (CLB, Configurable Logic Block) in the chip central committee according to the matrix arrangement, the chip all around for the programmable input/output block (IOB, Input/Output Block), between the CLB ranks and CLB and IOB has the programmable interconnection resources (ICR, Inter Connect Resource). CLB, IOB and ICR by distribute in the chip the SRAM static storage cell control, in the SRAM data decide FPGA the function, these data may when the system adds the electricity automatic or loads by the command control from the exterior memory.
When carries on the data storage, may read in directly the data in FPGA internal Block RAM, to a certain extent reduced the FPGA resource distribution. But FPGA the internal bringing RAM block is limited, when must carry on the large capacity data storage this limited RAM block is cannot satisfy the system design request by far. This time, needs to unify FPGA with exterior RAM completes the large capacity data storage. Concrete hardware circuit as shown in Figure one:
Figure one hardware circuit schematic diagram
3 IS61LV25616AL function synopsis
IS61LV25616AL is Integrated Silicon Solution Corporation (ISSI) a section of capacity for 256K×16, and pin function completely compatible 4Mb asynchronous SRAM, but is Xilinx Corporation’s Spartan-2E series FPGA provides the high performance, the high consumption ratio periphery memory. Besides 256K×16 asynchronous SRAM, ISSI also provides 128K×16, 512K×16, 256K×8, 512K×8 and 1M×8 asynchronous SRAM.
IS61LV25616AL pin structure diagram as shown in Figure two:
Figure two IS61LV25616AL structure diagram
3.1 chief features
(1) working voltage: 3.3 volts;
(2) access time: 10ns, 12ns;
(3) chip capacity: 256K×16;
(4) seal form: 44 pin TSOPII seal, also some 48 pin mBGA and 44 pin SOJ seal;
(5) uses 0.18μm the technical manufacture;
3.2 pin functions
(1)A0~A17:18 position address input line;
(2)IO0~IO15:16 position three states of matter data feeds output line;
(3): Writes the pilot wire;
(4): Selects patches or strips of land as worth saving for seed the signal;
(5): The output enables the signal;
(6)th: The low byte, the high byte enable the signal;
(3)~(6) pilot wire is the low level is effective.
3.3 control logic circuit design
As shown in Figure three, the control logic realizes by FPGA. Mainly includes reads the address producer, to write the address producer, the read-write clock signal producer and the read-write control and so on several parts. Below performs to narrate separately.
Figure three functional block diagram
(1) writes the address producer: Because designs time uses 256K×16 SRAM, therefore has 18 bit addresses, writes the address producer to realize with 18 counters. Actuates depending on the external clock, carries on after every time one time writes the operation, the read-write control unit produces the counter impulse, makes it to increase 1, counts until 18 counters circulates reads in the address is 0 spaces again completely.
(2) reads the address producer with on, also uses 18 counters to realize, according to the system request, every other certain sampling period will read the address pointer displacement certain displacement quantity, and from this position read data.
(3) read-write address selector as a result of read-write address multiplying base pin, therefore in read-write operation time, must select the corresponding address. This needs by the FPGA control chip on, and so on control signals to come to SRAM to carry on the read-write the operation.
(4) in addition, because between the read-write cut, in the data line data instantaneous like does not process in the cut can present the chaotic phenomenon. Therefore, to avoid reading, writing the operation to have the conflict, the data line assumes three conditions, reads the data, to write the data and the high-impedance state. From writes about in the process which reads to give in the data line to deliver the high-impedance state.
(5) when needs to carry on to SRAM writes the operation, by the FPGA control produces writes the address strobe signal, this gating signal is a single pulse mode, like the chart in the four, this pulse drops along triggers SRAM, informs starts to RAM to carry on writes the operation, causes FPGA to output writes the address, simultaneously gives in the data line to deliver the data. In writes operation period, selects patches or strips of land as worth saving for seed the signal maintains the low level throughout, but writes the address strobe signal rise along the arrival time causes to write the address counter to increase 1. Ex analogia, through writes the address strobe signal height level fluctuation to complete to the data reads in turn. What needs to pay attention, the address wire and the data line, simultaneously bestow on the new value for Gao Shike, but only then after changing low entrusts with in the data line the new value to be only then effective.
Figure four RAM writes the operation succession
Carries on to SRAM reads the operation to be relatively simple, is carrying on reads operation period, , is the low level throughout, is the high level throughout. Carries on one time to read the operation every time, the address changes one time according to the system request. Also pays attention, the address change time must be before the data change time. Figure five is RAM reads the operation succession.
Figure five RAM reads the operation succession
The following is a section the control RAM read-write operation succession procedure code which describes with the VHDL language:
OE_SRAM<=LOWLEVEL;
CE_SRAM<=LOWLEVEL;
when 0 => addr_SRAM<=temp_addr_SRAM; –WRITE to SRAM
data_SRAM<=data_in;
WE_SRAM<=’1′;
LB_SRAM<=’1′;
UB_SRAM<=’1′;
when 1 => WE_SRAM<=’0′;
LB_SRAM<=’0′;
UB_SRAM<=’0′;
when 2 => WE_SRAM<=’1′;
LB_SRAM<=’1′;
UB_SRAM<=’1′;
when 3 => WE_SRAM<=’1′; –READ from SRAM
LB_SRAM<=’0′;
UB_SRAM<=’0′;
data_SRAM<=b ” ZZ_ZZZZ_ZZZZ_ZZZZ_ZZZZ “; –Delivers for the data line in high-resistance
addr_SRAM<=temp_addr_SRAM;
when 4 => data_out <=data_SRAM;
In the procedure, when carries on the read-write operation, selects patches or strips of land as worth saving for seed enables signal CE_SRAM and the output enables signal OE_SRAM throughout is the low level.
· is carrying on the 0th time to the 2nd time writes the operation: 0th time address wire addr_SRAM and data line data_SRAM simultaneously bestows on the new value, pilot wire WE_SRAM, LB_SRAM, UB_SRAM must experience a narrow pulse the change process, RAM, in gains drops to this pilot wire after the information, apparent starts to carry on writes the operation. What needs to pay attention, although data, in the 0th time has bestowed on the data line, but because writes the operation is the pilot wire low level is effective, therefore in the data line has the data updating is truly after the pilot wire becomes the low level, therefore, in the data line actual renewal time is in the 2nd time.
· the 3rd, 4 conditions are carry on read the operation: In read-write transformation time, is also in the 3rd time as mentioned above must give in the data line to deliver the high-impedance state. Thus, reads the data the succession relations to carry on the control by the system clock, delivers the address which in the 3rd time for the address wire in must read, the 4th time sends out the data port’s on data. What here must pay attention, reads the data to compared to read address late one time. Thus, has completed to the exterior RAM read-write operation control.
4 conclusions
This system has applied in Lolan - in the C navigation receiver’s signal processing. The experiment proved that this design has completed the large capacity high speed asynchronous data storage stably reliably, further enhanced system’s performance.
