Abstract: W3100 is WIZnet Corporation specially the hardware TCP/IP agreement stack chip which promotes for the ethernet interconnection and the embedded equipment, its hardware TCP/IP agreement stack has contained TCP, UDP, IP, ARP and the ICMP agreement. In the article introduced the W3100A main feature, the pin function and the basic structure, have analyzed the W3100 software and hardware design application method.
Key word: TCP/IP agreement stack; W3100A; Socket API; Ethernet
1 W3100A synopsis
In recent years, along with the technical rapid progress, the electronic products toward miniaturized, intellectualized and the network direction developed. Realizes the ethernet interconnection in the small embedded equipment to become the research and the application hot spot. Under this kind of tidal current’s impetus, the researchers proposed many solutions. The traditional procedure is implants the TCP/IP agreement stack in the embedded equipment, or transplants one to have the TCP/IP agreement stack’s embedded operating system. Although the above procedure has made the good progress in many applications, but is take sacrifices the massive resources as the price. But this article introduced the W3100A hardware agreement stack may in take the extremely low system resources under the condition to complete the network communication fast.
The W3100A main performance characteristic is as follows:
* hardware agreement stack including TCP, IP Ver.4, UDP, ICMP, ARP;
* support hardware ethernet agreement DLC and MAC;
* simultaneously supports four group independent network connections;
* supports the Ping order;
* the protocol processing speed achieves full-duplex 4~5Mbps;
* supports Intel/Motorola the MCU bus interface;
* supports the I2C connection;
* has the standard MII connection, may connect the first floor ethernet connection chip;
* may provide Socket API to accelerate the application procedure development;
* supports the full-duplex pattern;
* among them constructs 16KB pair of mouth RAM to be possible to take the data buffer;
* uses 0.35μm the CMOS fabrication technology.
2 W3100A pin functions
W3100A uses 64 foot LQFP seal, its pin distribution as shown in Figure 1. Various pins functional description is as follows:
TXD[0]~TXD[3]: In the TXD_CLK rise along transmission data. When serial pattern, TXD[0] serves as the serial data transmission pin, TXD[1]~TXD[3] is invalid.
TXE: The transmission enables the end.
TXD_CLK: The data transmission clock, the clock provides by the ethernet connection chip.
RXD[0]~RXD[3]: Drops in TXD_CLK along the receive data. When serial pattern, RXD[0] takes the serial data receive pin, RXD[1]~RXD[3] is invalid.
RXDV/CRS: Carrier monitor. The high level is effective.
RXD_CLK: The data receive clock, the clock provides by the ethernet connection chip.
COL: Conflict survey pin. Has the conflict when the half-duplex pattern effective.
A[14~8]/DA[6~0]: In the MCU bus interface pattern mean is 14~8 bit addresses. In the I2C pattern mean is the I2C connection 6~0 device addresses.
A[7~0]:7~0 position address wire.
D[7~0]:8 bit data line.
INT: Receive transmission interrupt request. The low level is effective.
CS: Selects patches or strips of land as worth saving for seed the signal. The low level is effective.
WR: Writes a letter the number. The low level is effective.
RD: Reads the signal. The low level is effective.
RESET: Reset signal.
CLOCK: Work clock. Usually provides by the ethernet connection chip, the recommendation frequency is 25MHz.
EXT_CLK: External clock input signal.
LINK: Expressed whether to have connected the ethernet. The low level expression connection is effective, the high level expresses the TCP overtime or the connection closure.
SERIAL:10BASE-T SERIAL or NIBBLE choice.
FDPLX: Full-duplex/half-duplex choice. 0 are the full-duplexes, 1 is a half-duplex.
MODE[2~0]: Uses in choosing the W3100A working pattern. 000 are the clock patterns; 001 are the external clock patterns; 010 are the non-clock patterns; 011 are the I2C patterns; 1xx is the test pattern. 3 W3100A internal structures
The system design personnel may facilitate using W3100A quickly for the product increase network function. The W3100A hardware TCP/IP agreement stack has contained TCP, UDP, IP, ARP and the ICMP agreement. And supports a set with Windows system same socket API. W3100 internal structure diagram as shown in Figure 2.
W3100A altogether has the 32kB internal memory space. And was located at the memory crown address is the 0×0000~0×01FF 1kB space allocation has given the control register group, 0×2000~0×3FFF as retention space supplies other equipment use, but 0×4000~0×5FFF was the transmission buffer, 0×6000~0×7FFF was the data receive buffer. Because W3100A may provide 4 group independent bridging forehearths for the user, therefore corresponds the 8kB transmission buffer and the 8kB receive buffer may carries on the disposition through register TMSR and RMSR. Collocation method as shown in Figure 3.
4 using design
4.1 hardware designs
W3100A has 3 kind of different working patterns, respectively is Direct Bus the I/F pattern, Indirect Bus the I/F pattern and I2C Bus the I/F pattern. The user may act according to own actual situation to carry on the choice. Below pattern and I2C Bus the I/F pattern does on commonly used Direct Bus the I/F by the simple introduction.
Figure 4 is Direct Bus the I/F pattern hardware architecture diagram.
The figure shows, under this pattern, W3100A used in common 15 address wires, 8 bit data lines, to select patches or strips of land as worth saving for seed CS, and read-write control signal WR and RD. It is not difficult to see, under this pattern the hardware circuit design is relatively simple, but must take the many MCU resources. Simultaneously should also pay attention, in Direct Bus under the I/F pattern, the W3100A work clock also has 3 kind of different patterns, in the majority situations, the system recommendation uses the Clocked pattern, because under this pattern the system may stabilize work. But if in the system the MCU access speed is smaller than 100ns, should be the W3100A independent external connection clock and chooses External the Clock pattern. But when MCU CS, RD, the WD signal succession satisfies W3100The request, may also not want the clock.
Figure 5 is I2C Bus under the I/F pattern, MCU and W3100A connection schematic drawing.
I2C Bus under the I/F pattern, may use SCL and SDA between MCU and W3100The serial transmission data, clock holding wire SCL provides by MCU, SDA uses for between MCU and W3100The transport address and the data. So long as in system’s MCU supports the I2C main line then to use this pattern. May see, uses this pattern to be possible to reduce MCU and the W3100A ties massively, thus saves MCU the resources.
4.2 software designs
In addition, through WIZnet Corporation is Socket which W3100A provides specially the API software, may cause the network communication the software design to be more convenient. Carries on the design when using this software, should the first initialization W3100A network settings, namely establish the default gateway, the subnet mask, this aircraft physical address and the IP address in the corresponding register, then establishes the Socket connection to realize the communication. The entire process and Windows the Socket programming is very similar, here no longer gives unnecessary detail.
5 conclusions
W3100A has the transmission speed to be quick, work stable reliable, system expenses small and so on merits, may provide the very good network solution for the small embedded equipment.
