Abstract: PM8316 is one kind of low power loss which, the high performance multi-channel E1 mapping multiplying framing chip PMC-Sierra Corporation produces. This chip interior integrated the mapping, the multiplexer, the framing, its handling capacity is 63 group E1, and includes 8 microprocessor bus interface and 5 standard signal JTAG test port, may support the receiving and dispatching vibration weaken. In the article introduced the PM8316 major function and the connection, have given it in the SDH terminal device’s main signal circuit diagram.
Key word: SDH; PM8316; Only Holland; Expenses
1 introduction
Synchronized digit series SDH takes the new generation synchronization digital hierarchy standard, compares with traditional orbit digit series PDH has the network architecture to be nimble, network management ability and self-recovery ability are formidable, interface specification standard, around compatibility good and so on merits. Therefore, in the telecommunication network to the network, intellectualized, under the integration trend of development, SDH is substituting for PDH gradually day by day. SDH has the backward compatibility, i.e., the extant PDH three great series various speeds rank’s signal can integrate SDH in the transmission module, like this enables the extant PDH equipment also to continue to use, does not send creates the waste. But this kind loads the PDH signal and each kind of new service the SDH signal space, and constitutes the SDH frame process to be called the mapping and the multiplying process.
In SDH, the mapping is refers to the PDH signal bit process certain corresponding relationships lays aside to the SDH vessel’s in exact location comes up, for example byte synchronization mapping; The multiplying is refers to several group signal internodes inserts gathers is a group signal process word by word. Shown in Figure 1 is the SDH multiplying mapping structure which China stipulated that through the standard agreement, may three speed PDH signal mapping multiplyings to synchronized transmission module STM-N.
PM8316 is satisfies PDH 2Mbit/s or the 34Mbit/s information flow and between the SDH STM-1 information flow mapping multiplying reconciliation mapping multiplying chip.
2 PM8316 main features
PM8316 has the following main feature:
* provides 19.44 MHz or 77.76MHz the SDH minute inserts the multiplying correspondence bus interface, may with PMC-Sierra Corporation’s other SDH equipment seamless connection.
* the support maps 63 group E1 data streams from 155Mbit/s STM-1 most solutions, and simultaneously 63 group E1 data stream multiplying to STM-1.
* the system side connection supports 8Mbits/s the H-MVIP main line, simultaneously provides 8Mbits/s along with the road signaling and altogether the road signaling channel.
* support receive and transmitting branch’s vibration weaken.
* supports the E1 far-end block, CRC-4, the frame position wrong performance monitor.
* fixed time provides 3 non-vibrations for the system the restoration clocks.
* provides each link diagnosis and the line circle returns.
* provides the PRBS generator and the detector on each leg, uses in testing wrongly.
* for the disposition, the control and the condition monitor provides a 8 microprocessor bus interface.
* provides standard 5 signal P1149.1 for the boundary scan test the JTAG test port.
* uses low power loss 1.8V/3.3V the CMOS craft. All base pins are the 5V pressure resistance.
3 PM8316 interface functions
PM8316 functional module as shown in Figure 2, what it in view of is China’s correspondence standard.
The PM8316 chip provides the line end connection, the observation connection and the system end connection. The following separately makes the brief introduction to each connection and the receiving and dispatching function.
3.1 line end connection
PM8316 provides 19.44MHz or the 77.76MHz correspondence bus interface may withdraw the localization series with phototiming Holland the chip to carry on the seamless connection only, its main line width is 8. When main line work in 19.44MHz, corresponds when the main line capacity supports STM-1 most much, the data transmission, each data clock to data sampling one time; When main line work in 77.76MHz, corresponds when the main line capacity supports STM-4 most much, the data transmission, every 4 data clock to data sampling one time. Which one kind of frequency no matter PM8316 is in the working pattern, this chip’s message capacity is STM-1.
3.2 observation connections
Observation connection including the JTAG connection and microprocessor connection. The JTAG connection supports the boundary scan and 5 standard JTAG instructions; The microprocessor connection is one has 13 address wire 8 bit data and the mouth, it has provided the normal pattern register which the massive normal works need and strengthens the testability test pattern register.
3.3 system end connection
It contains two kind of main lines: High density multi-factory integration agreement main line H-MVIP and band width adjustable interconnection main line SBI. The H-MVIP main line may simplify and the link level equipment’s connection greatly, it may provide 63 group E1 all time slots, along with the road signaling or altogether the road signaling connection; The SBI main line is a 8 bit parallel main line, its message capacity, correspondence main line capacity and work clock way with line end connection.
3.4 receiving and dispatching functions
Speaking of the system end, has transmits and receives two different directions, below aims at these two directions to give the introduction to the respective signal processing flow.
In the sending terminal, take H-MVIP as the form E1 signal first after the H-MVIP clock and the frame synchronization clock sampling receive is sent in buffer memory ELST. Then carries on after ELST is controlled glide processing enters the framing, in the PCM class which restores searches for the base frame synchronization and the CRC multiframe synchronization again by the framing, and coordinates the transmitter to have the 2048kbit/s data stream according to the ITU-T standard, simultaneously produces the base frame and the CRC multiframe to each group E1. After like on processes, the data stream then entered the leg byte synchronization mapping, 3 leg byte synchronization mapping each most may map 21 group E1 class a TUG3 only Holland. In order to report the performance monitoring result, through the establishment, the far-end warning processing display may cause V5 8th and 4th expresses the far-end flaw instruction and the far-end failure indication separately. What if on completes is channel Holland processes only, to further map, transmits the leg path overhead processor is 21 group E1 production path overhead, and calculates in current leg synchronization only purse SPE BIP-2, in the computed result insertion next leg SPE V5 BIP-2 position, simultaneously also will insert again the far-end block mistake, the far-end defeat instruction and the far-end error instruction. Finally processing which produces after the leg only Holland processor’s in Dutch buffer and the indicator only forms SPE.
Is upward in the receiving end, in 3 leg only Holland processor’s take TUG-3 TU-12 as the processing object 熇 with the path overhead H4 byte, monitors the multiframe in-step condition, the indicator to explain that the Dutch buffer, the indicator to produce and so on only in turn, afterward decides leg path overhead byte V5 in the buffer storage output class position. In the receiving branch path overhead processing part, 3 leg path overhead processor surveillance leg Holland processor’s output class, simultaneously calculates the bit to insert the parity check and compares with the V5 BIP-2 code only, if the comparison result is different, explains the transmission to contain errors, and to carries on the accumulation wrongly. In the receiving branch byte synchronization solution mapping part, may the STM-1/VC4 in Dutch TUG3 solution mapping only be 21 group E1. Afterward using the receive digit vibration attentuator, provides the quite good vibration allowance and the vibration weakens, when the vibration frequency is bigger than 5Hz, the vibration attentuator can hold 48UIpp the input jitter, when the drifting frequency is smaller than 5Hz, the vibration attentuator can remain the vibration by every 10 time of 20dB standard to carry on the weaken. After finally will solve mapping reconciliation multiplying processing signal from buffer memory ELST by H-MVIP form output.
4 model applications
The PM8316 function is formidable, may use in SDH dividing inserts the multiplying equipment, the terminal multiplying equipment, the digital cross-connect equipment, the light interface equipment, the digital modulation demodulator and the router and so on many kinds of equipment. Below explains PM8316 through an actual light interface system’s example the application.
Shown in Figure 3 is by the PM8316 constitution light interface circuit diagram, this electric circuit mainly transforms module HFCT-5205, expenses indicator processing module PM5342, the mapping solution mapping processing module PM8316 constitution by the electro-optic. This system may be SDH and the PDH two big standard communication system provides the simple connection bridge, and 煟 stops Zheng Sangxiao in the system end by the multi-factory integration agreement 牭 male to ask that the sword may most achieve the high and low 63 E1 link, if the system end increases other functional module again, may construct the ingredient to insert the multiplying equipment and the terminal multiplying equipment. They constitute the electric circuit has the connection to be simple, the function formidable, easy to debug, to manage and so on characteristics easy. Below gives the explanation by the module division to partial signal’s processing.
Electro-optical/electric light transformation module: Constitutes by HFCT-5205, it will receive the light signal transforms for the electrical signal gives PM5342, simultaneously the electrical signal which will come from PM5342 will transform into the light signal. It and the PM5342 connection are the 155MHz differential interfaces. Moreover, has provided signal loss signal SD for the warning indication.
Expenses indicator processing module: Constitutes by PM5342, in the receive side, completes the clock recovery, the string and transforms, regeneration section expenses processing, multiplying section expenses processing, high low-order path overhead processing, the high low-order indicator explanation and the buffer localization and so on. In the transmission side, the processing sequence is opposite. With the PM8316 connection is the correspondence bus interface.
Mapping solution mapping module: Constitutes by PM8316, mainly completes mapping/functions and so on solution mapping, multiplying/demultiplexing, framing, the nuts and bolts in the above component introduced that mentioned.
May realize the following 4 signal processing function through CPLD:
(1) is PM5342 and PM8316 provides the receive and transmission data clock 19.44MHz. The 19.44MHz clock signal which produces by the crystal oscillator sends in CPLD first, then transparently transmits on many out-ports in CPLD, takes in this system all 19.44MHz clock’s origin.
(2) frame pulse production. In this system, needs respectively is PM5342, PM8316 produces DFP, the LAC1 symbol signal. When DFP is the high level, indicated that each first synchronized purse appeared only, the counter which recently the PM5342 interior has a basis because to receive DFP which adjusts, therefore it is not unnecessary to appear in any frame; LAC1 expressed that 煟 punishes the sea in LADATA by 犐 the mill you value curtain frame and the multiframe boundary, when contains has in 4 base frame’s multiframe’s first frame’s first C1 byte appears, its high level is effective. They are the rise along the sampling. Therefore when produces the frame pulse, needs the drop along the sampling, moreover they are every 4 base frame produce a frame pulse, therefore the count cycle is 270 (row) ×9 (line) ×4 (frame) =9720. The following is the part VHDL code:
if f19mc = ‘ 0 ‘ and f19mc’event then
if count =9719 then
LAC1 <= ‘ 1 ‘;
DFP <= ‘ 1 ‘;
count <= 0;
else
count<= count 1;
LAC1 <= ‘ 0 ‘;
DFP <= ‘ 0 ‘;
end if;
end if;
(3) the frequency division produces the CTCLK clock. Because this system end uses the MVIP connection, therefore CTCLK must locate in CMVFPB. Also considered the crystal oscillator produces 19.44MHz clock and this frame synchronization clock not related phase relation, therefore uses CMVFPB to obtain CTCLK to the CMV8MCLK reset direct frequency division. The following is the part VHDL code:
if cmvfpb = ‘ 0 ‘ then
count <=3;
outclk<= ‘ 0 ‘;
elsif (cmv8mclk ‘ event and cmw8mclk = ‘ 1 ‘) then
if count =7 then
outclk<=not outclk;
count <= 0;
else
count <= count 1;
outclk<=outclk;
end if;
end if;
ctclk<=outclk;
(4) closed circuit and by-pass. In the system end, the link, MVI/ED, between the purse, the E1 index relations are only as follows:
LINK #=4× [MVI/ED index-7× (SPE-1) - 1] E1
May know by the above equation, in MVI/ED the index number is in 6, 13, 20 channels only then 1/4 band width is used, to raise channel’s use factor, may not synthesize many full load channels to a channel on, this treating processes are called as the closed circuit. Otherwise, the opposite process is called as the by-pass. In this system, must realize 3 channels (MVID[6], MVID[13] and MVID[20]) to a channel HMVIDC closed circuit, with channel HMVEDC to 3 channels (MVED[6], MVED[13] and MVED[20]) by-pass. In realizes in process, because the closed circuit and the by-pass processing each channel’s data rate is the same, therefore in the treating processes only need wait for and the detention then.
5 conclusions
This article introduced special-purpose multi-channel E1 mapping multiplying framing chip PM8316, it will map the multiplying function and the framing function combines, therefore in time design same capacity system, PM8316 may simplify the system structure compared with other components, reduce the power loss greatly, simultaneously may simplify debugging step, the reduction research and development cycle.
