Along with each kind of electric circuit and the chip performance (speed, integration rate and so on) enhance unceasingly, particularly in the military, the aerospace urgently needs to the reliable request often is on the way first, the people increase day by day regarding system’s reliable aspect’s request, this set the strict goal request to circuitry’s design and the manufacture.
The memory is in the circuitry one of most commonly used components, uses the large scale integrated circuit memory chip constitution. The actual statistics indicated that memory’s is wrong (is also called single event in outer space application major fault by the transient state to disturb, SEU) causes dislocated [1] or is related the multi-dislocations, but the stochastic independent many mistakes are extremely few. Semi-conductor memory’s mistake divides into on the whole hard wrong and soft wrong, mainly for soft wrong. Hard wrong displays the phenomenon is in some or certain positions, deposits and withdraws the data redundancy to present the mistake. Presents this kind of phenomenon the reason is or a several memory cell presents the breakdown. Soft wrong is mainly causes by Alpha the granule. In the memory chip’s material includes the trace-level activity element, they will release Alpha the granule interrupted. These granules by the quite big energy impact storage capacitance, change its electric charge, thus causes the stored datum mistake. Causes the soft wrong another reason is the noise jamming. Meanwhile under the outer space environment, under the charged particle enough energy hit, in memory’s memory cell’s position has the turn over, thus produces SEU wrongly [2]. This article designed has realized and investigates the error detection chip with the CPLD technology to carry on to the memory fault-tolerant, enhanced system’s reliability greatly. Below is specifically the fault-tolerant memory and the gate police guard electric circuit’s design.
1 error detection and error correction principle
(As soon as commonly used can examine at the same time 2 dislocations to be able to correct 1 dislocation i.e. to investigate examines two, SEC-DED [3, 4]) the error correcting code has the expansion hamming code (Extended Hamming Code) and the best wonderful weighted code (Optimal their most digits is apart from is 4, both have the similarity, if the redundance is the same, regarding data figure k, verification figure r should satisfy 2 r-1 ≥k r. When k=16, r=6, the data position long increases 1 time, the verification figure only need increase 1, the coding efficiency is high. Moreover says from the origin, both respectively are the hamming code expansion code and the shortened code, also some material call the best wonderful weighted code the revision hamming code (Modified Hamming Code). The literature [4] introduced SEC-DED and SEC-AUED) the code arranges the decoding theory. From the performance looked that the best wonderful weighted code is more superior than the expansion hamming code, the former is investigating the error detection ability aspect also to surpass the latter, his 3 wrong investigate the probability to be lower than the latter by mistake, but 4 wrong detection probabilities are higher than the latter, most importantly he is advantageous for the hardware to realize, therefore application most, this article uses the best wonderful weighted code.
First constructs the best wonderful weighted code the check matrix is the H matrix, the best wonderful weighted code’s H matrix should satisfy:
(1) each row includes odd number 1, and not same row.
(2) total 1 integer are few, therefore the verification position, follows in the type production expression partly to add the number of terms to be few, thus production logic needs the two-input adder are few, may save the equipment, reduce the cost and to enhance the reliability.
(3) each line of 1 integer is as far as possible equal or the close some mean value, this kind of decision production logic and progression uniformity, not only the decoding speed is quick, simultaneously the line is symmetrical.
In the application uses (13,8,4) best wonderful weighted code, the data code for (d7 d6 d5 d4 d3 d2 d1 d0), the verification code for (c4 c3 c2 c1 c0), the P matrix and the coding rule respectively is:
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When decoding codes the new verification position which once more data obtains with original verification position mold 2 Canada, then obtains follows type S, by its may distinguish the wrong type:
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1), if S=0, then thought that does not have the mistake;
(2) if S≠0, and S includes odd number 1, then thought that has had the single dislocation; If S≠0, and S includes even number 1, then thought that has had 2 dislocations.
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Therefore, wrong pattern S= [s 0 s 1 s 2 s 3 s 4] with the mistake 11 correspondences which produces, as soon as thus realizes investigates examines two functions.
2 memory fault-tolerant chip design realizes
2.1 memory designs realize the plan
(1) backup line (or row) plan
This kind of plan is increases certain backups in the memory chip design and the process of manufacture the line (or row). When chip testing, if discovered expires line (either row), through laser (or electricity) processing, (or row) replaces with the backup line. This method’s merit is the design is simple, the tube core area increases few, the electric circuit speed has not lost. But, he needs to increase certain tests and the revision actual effect line (or row) the craft link, a more important weakness is this kind of plan is only suitable for RAM, cannot use in ROM.
(2) error correction code scheme
This kind of plan is uses the error correction code in the memory chip interior, the automatic detection and corrects the mistake. This plan does not need extra craft links and so on test and correction mistake, besides raises the rate of finished products, but also has the obvious improvement to the reliability. This kind of plan most prominent merit is especially qualify ROM; In may also use in RAM to the speed request not high situation. His major object lies in must take the extra chip area, simultaneously because of arranges the decoding to affect the chip entire working speed. Will use in the memory system-level the error correction code and so on the fault-tolerant technical introduction memory chip, is raises the memory chip rate of finished products and the reliable effective action. For example in the server uses the ECC memory has used this technology.
This article fault-tolerant memory uses the error correcting code plan, it realizes diagram as shown in Figure 1.
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2.2 investigate the error detection circuit design
Investigates the error detection electric circuit to coordinate CPU the read-write succession to carry on the work, may divide into the CPU succession the read cycle and the write cycle. When write cycle, the main line reads in directly through the error correction electric circuit the data the memory, simultaneously the data has 5 b verification code through the error correction electric circuit to read in the redundant memory. Read cycle becomes 2 steps, 1st step reads the data and the verification bit data separately from the memory and the redundant memory sends in the error correction electric circuit lock to save; 2nd step-by-steps conducts wrong, if does not have the mistake to send out directly the data the data bus, some 2 dislocations have the interrupt to carry on processing, some 1 dislocation carries on to the data corrects error and sends in the data bus. What because needs is the correct data, if is verifies the position to make a mistake, then does not carry on any processing, direct output correct data.
2.3 electric circuit input output design
RD, WR, CLK is CPU inputs to investigates the error detection signal, produces the chip through the control circuit to control from the inside the system signal. When writes a letter the number, DB [7..0] from the data bus input, will save through the lock later (the Santai module) reads in the memory after the three-state control, simultaneously the data will produce module (Paritygen) through the verification code to have 5 b verification code, will read in the redundant memory through the three-state control. When reads the signal, the memory data read-in investigates the error detection electric circuit saves after the lock to have 5 b verification code, simultaneously with 5 b examination code which reads from the redundant memory together through wrong pattern module (Errorsample), has the wrong pattern. Through wrong pattern examination mistake, when the data makes the mistake after the error correction module (Errorcorrect) error correction correct data output data bus. Errordetec is the error status module, SEF, DEF is the error status signal. 0,0:00 correctness, 1,0:00 1 dislocation, 1,1:00 2 dislocations. The electric circuit realizes various part of functional module as shown in Figure 2.
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3 simulations and profile
This article uses Altera Corporation’s CPLD component EPM7128 to take the design environment [5], Figure 3 investigates the error detection circuit simulation graph, realizes with CPLD investigates the error detection circuit simulation, in the chart when 118~205 ns from the data line when write data AA,359~443 ns the simulation read when the data has 1 dislocated situation, when 601~692 ns the simulation has had 2 dislocated situations, this time examined 2 dislocations, but could not correct. when 781~863 ns the simulation verification position has had time 1 dislocated situation.
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4 analyses and conclusion
This article uses the best wonderful weighted code the basic principle design error correcting code electric circuit to be possible to adjust the single dislocation, picks out 2 dislocations, the memory does not interrupt the work because of the single dislocation, therefore its mean time between failure MTBF increased, enhanced the reliability. As soon as but investigates examines two yard additional equipments to cause MTBF to drop.
In the efficiency, is located in time T, has 1 dislocated number of times is n 1, has 2 and the multi-dislocated number of times is n 2, when uses the error correcting code, the mean time between failure is T 1 =T/(n 1 n 2), after using the best wonderful weighted code, 1 dislocation is may investigate, only 2 and the multi-dislocations may not investigate, takes the error handling. Supposes as a result of uses the error correcting code to increase equipment δ%, thus after using the best wonderful weighted code the mean time between failure is:
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According to the material estimated that occupies entire wrong proportional gain G=4.6~9.3 regarding
1 dislocation. Realizes memory’s fault-tolerant through CPLD, reduced the design development cycle greatly, reduced the cost, simultaneously enhanced system’s reliability.
