The introduction μPSD memory system internal structure and the collocation method, discussed have been related the PSDSOFT software the application method.
Background
If μPSD the component has to ST Corporation understood certainly, the familiar MCS-51 series monolithic integrated circuit’s internal structure and the principle, have used PSDSOFT EXPRESS and the KEIL development design, to will understand that this article has the very big help.
The MCS-51 monolithic integrated circuit uses the Harvard structure the system structure, namely the data-carrier storage space and the program memory space is mutually independent. It has 16 address buses, biggest addressing ability is 64K, this decision procedure or the data space cannot surpass 64K. The above two spots are this article all discussion’s premise foundations.
μPSD memory system structure
μPSD (programmable system component) constitutes by the standard 8032 nuclei and ST Corporation’s PSD, the memory system contains two main parts; first, 8032 internal memory resources: 256B internal RAM and 128B internal special function register SFR; Second, in PSD memory module: The main/FLASH memory, expansion SRAM and controls PSD CSIOP (Chip-Select I/O Port, is similar in 8051 SFR). μPSD host/FLASH is the identical storage medium (in the early PSD813F1 secondary storage is the EEPROM structure), is two independent memories. Advocates FLASH to pass destiny 4~8, each 16~32kb; FLASH passes destiny 2~4, generally each is 8kb. μPSD uses decodes the programmable decoding logic array (DPLD), page register PAGE, memory control register VM, realizes jointly to the memory system’s disposition.
About IAP and paging technique
Why μPSD can have two FLASH? Puts briefly, this is to realize IAP to design. IAP is “programs or the promotion code in the application”, its principle is: The monolithic integrated circuit Chinese dress has a set of user program and a set of code refresh routine. In normal condition, what monolithic integrated circuit movement is the user program; When needs the procedure promotion, the system will cut the code refresh routine, will download the new user program code unguardedly through the serial port or other, and will read in the original user program memory, after the renewal will complete, will then cut to the user program. Based on the MCS-51 system structure characteristic, moves the master routine in the identical memory and the rewriting procedure is impossible to realize. All realizes the IAP function system with MCS-51 to have two independent memories. Realizes the IAP difficulty to lie in memory’s hand-off control, how manifests in μPSD is mainly to use the VM register as well as how to select patches or strips of land as worth saving for seed the control to the memory.
In addition, is getting higher and higher along with the application request, the word length increases unceasingly, the 64K limit already became in the design the bottleneck. Many soft/hardware suppliers by might and main promote their plan to realize MCS-51 to be bigger than 64K the support, the paging technique arise at the historic moment.
In the paging design most important is the public area and the paging area establishment, the so-called public area is in all pages is an effective memory area. In the procedure space, the 64K scope (1 page) in procedure is continual, once surpasses this scope, will only retain low 16, the highest order will be discarded, the procedure will meet the rebound to start place the movement. Guaranteed the procedure when the page cuts “will not run flies” will be realizes through the public area. The paging technique realizes the method is: When procedure when transfer located at paging area procedure, first preserves the return address, then the extension jumps to the public area execution, revises the page register to realize page’s cut again to the new page number, the calling program, returns to the public area, restores the original page number, finally from preserved return address returns.
The public area’s size establishes voluntarily by the user, in μPSD usually uses in main/FLASH or many achievement public areas, if uses 1 FLASH is 8KB,2 block FLSAH is the 16KB,1 block advocates FLASH is 32KB, if only wants to use advocates in FLASH 20KB to make the public area is also feasible, so long as will advocate the FLASH address range only definition will be the 20K scope may. Certainly, the public area’s size cannot surpass 64K. The public area must be located in the 64K scope the low end, this is because of the MCS-51 interrupt entry point address reason. In the public area preserves all common subroutines, the interrupt service, the overall situation chart as well as system’s initialization part and the page cut procedure.
μPSD memory’s spatial disposition
μPSD the memory system disposition is mainly to the procedure space establishment, relatively speaking data space’s disposition is slightly simple a spot. μPSD main/FLASH may establish as the procedure or the data space, this is by the VM register decision, VM register’s function as shown in Table 1. The VM content may when the movement makes the revision by MCU, this realizes the IAP key. May suppose buyer/FLASH in the PSDSOFT software flow is the procedure, the data-carrier storage or the procedure/data mixing memory, in fact is time the electricity default value carries on the establishment to the VM register on, in other words, is in the determination when the electricity main/FLASH is located at any space separately.
Table 1 VM register each function
In the table, “#RD may/not be able to visit” refers to this memory whether to be located at the data space, “#PSEN may/not be able to visit” refers to this memory whether to be located at the data space, because is carries on the discrimination in the MCS-51 system visit to exterior data/procedure space’s through #RD and #PSEN. Explaining with examples:
VM=0CH, indicated that advocates FLASH located at the procedure space, FLASH located at data space;
VM=16H, indicated that advocates FLASH located at the data and the procedure space, FLASH located at procedure.
The position 0 use for to assign SRAM whether to be located at the procedure space, because SRAM is only effective in the data space. The position 7 use for to instruct that the peripheral device IO pattern the permission with forbids, will introduce specifically in behind. Figure 1 may help to the VM register function understanding.
Figure 1 μPSD memory system structure
As shown in Figure 1, the VM position 0~4 with #RD, #PSEN realize jointly to main/FLASH and the SRAM choice. Here is allows the #OE signal through the output to carry on the control, even if i.e. memory’s address effective (CS effective), if #OE is invalid, also cannot visit this memory’s content. Main/FLASH #OE has two effective input items, 3/4 controls #RD by the VM position whether to have an effect, VM 1/2 controls #PSEN whether to have an effect. After VM each determination, may depend on Figure 1 to draw simplified the disposition structure. Here #OE signal is to main/FLASH each at the same time effective.
When realizes IAP, realizes through VM to the main/FLASH space carries on trades, for example, advocates FLASH to make the user program, FLASH serves as the promotion procedure; When normal work, advocates FLASH to make the procedure space, the movement user code, when carries on the procedure promotion, is going to the FLASH cut to make the procedure space, and moves in the FLASH promotion procedure, advocates FLASH to trade again the data space, to advocates in the FLASH user code to carry on the renewal.
μPSD memory’s address disposition
μPSD must observe the following rule to the memory allocation:
Rule 1. host/FLASH the block FS0~FS7, CSBOOT0~CSBOOT3 address range cannot be bigger than its physical size;
The rule 2. advocates FLASH between block FS0~FS7 the address not to be able to overlap;
Rule 3. FLASH between block CSBOOT0~CSBOOT3 the address cannot overlap;
Rule 4.SRAM, I/O, the peripheral device I/O address cannot overlap;
The rule 5. advocates FLASH, FLASH and SRAM, I/O, peripheral device I/O, if the address overlaps, the memory effective priority is SRAM, I/O, peripheral device I/O is highest, the FLASH next best, advocates FLASH to be lowest.
In the PSDSOFT design, if will violate the rule 2, 3, 4 to present the mistake, must revise can carry on the next step; But will violate rule 1 to issue the warning, if will neglect must certainly be careful. The rule 5 belong to the explanation rule, will not propose any prompt, in the attention address overlap situation the priority low memory cannot visit.
μPSD carries on the assignment through DPLD to each memory’s address, DPLD structure as shown in Figure 2.
Figure 2 DPLD structure
DPLD includes “and” the array and “or” the array, “and” in has an input item of altogether 57 item, “or” in has an output item of altogether 16 item. An input expression may participate in the address decoding the signal, the output item of namely each memory’s CS signal.
In what the DPLD input item is most commonly used is A0~A15, page register PGR0~PGR7,#RD, #PSEN, #WR, ALE. PDN is when the power management uses, if joins PDN in the address, expressed when the power source is effective the address decoding is only then effective, usually this item is joins automatically, the user may not use the tube.
The DPLD input item and the output item is not to dispose completely. To μPSD when the memory carries on the address disposition, a most important principle is “does not surpass 64KB not to want the paging, has not used the block does not need to dispose”. Has not used all memories regarding the small project, does not need to dispose, like this both simple, reduces makes a mistake, and convenience debugging and inspection. Besides CSIOP is which must dispose, other items may according to need to carry on the disposition.
PSEL by the peripheral device I/O mode control, under the PIO pattern, PA mouth all I/O is established as the three states of matter, the bidirectional MCU data buffer way, is somewhat similar with the MCU P0 mouth. In DPLD must state that PSEL0 and/or the PSEL1 actual address scope, when visits this address, the PA mouth enters the PIO way. Front states in the VM register 7th is the PIO pattern permission/inhibit control, PIO pattern internal control structure as shown in Figure 3. In order to avoid the scope which PSEL0 and PSEL1 assign in the procedure/data space being effective, should joins in PSEL0 and PSEL1 “! #PSEN” the signal, guaranteed the PIO pattern only when visits the data space effective.
Figure 3 PIO pattern internal control structure
Uses PSDSOFT for μPSD to carry on the disposition and the programming
μPSD PAGE is 8 registers, most may realize 256 pages, the PAGE register and the address range disposition is simultaneously has an effect. If in your system no matter were the procedure or data-carrier storage’s design has surpassed 64k, must want the paging. μPSD PAGE register’s 8 may use independently, may define in PSDSOFT is two ways, namely PAGING and LOGIC. PAGING is takes the paging use, LOGIC takes the general logical input function, is similar in PLD node NODE, or in CPLD great MACRO. When achievement PAGING, must start from the most low position, to use N to take PAGING, may realize the 2N page’s assignment, namely in memory’s address disposition has a 2N page to be possible to choose. Use as LOGIG when must start from the top digit to use, may define a name as it, may serve as DPLD the input item. MCU when movement may carry on to PAGE reads/writes the operation, but cannot according to the position operation, i.e. probably shield first revises again.
When the procedure and the data do not surpass 64K, does not need the paging, PGR0~PGR7 not to participate in the decoding. In present’s PSDSOFT software does not request the user to write the address equation again, only needed to fill in the address range to be possible. When does not use the paging, selects patches or strips of land as worth saving for seed PGAE NUMBER cannot fill in any value, if fills in “0″, then expresses located at the page 0. Is very simple in PSDSOFT to the public area’s establishment method, so long as did not fill in takes the public area the memory to select patches or strips of land as worth saving for seed “PAGE NUMBE” to be possible.
μPSD memory disposition example
As this article conclusion, gave a typical μPSD application example, the reader may refer to its memory’s disposition plan.
The use μPSD3234A-40U6 component, serves as FS0~FS7 the procedure/data-carrier storage, the address in 8000H~0FFFFH, is located at the page separately 0 to the page 7; CSBOOT0~CSBOOT3 as the program memory, takes the public area, the address is 0000H~7FFFFH. Expands SRAM to be located at 7F00H~7FFFH located at 0000H~1FFFH, CSIOP, the user I/O space definition is 7E00H~7EFFH.
Such memory disposition can satisfy the majority paging projects the design requirements, has used μPSD all memories, not only has maximized the procedure space and the data space, can also realize the IAP function. In this plan the procedure space may reach 256K 32K, the data space is 256K (FLASH) 8K (SRAM). The user may act according to the practical application project to dispose makes the simple revision, does not remove the use memory disposition.
If in the user project requests to realize IAP or to advocates the FLASH data-carrier storage to make the cleaning/revision, please certainly must pay attention, the promotion code or carries on the cleaning/revision operation to FLASH the procedure to put in the public area, namely in FLASH.
